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MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT

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Date Issued:
2005
Abstract/Description:
Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
Title: MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT.
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Name(s): CUI, ZHI, Author
Liou, Juin J., Committee Chair
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2005
Publisher: University of Central Florida
Language(s): English
Abstract/Description: Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
Identifier: CFE0000476 (IID), ucf:46360 (fedora)
Note(s): 2005-05-01
Ph.D.
Engineering and Computer Science, Department of Electrical and Computer Engineering
Doctorate
This record was generated from author submitted information.
Subject(s): MOSFET
reliability
lifetime
Hot-Carrier
modeling
RF
Verilog-A
simulation
RF
Cadence
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0000476
Restrictions on Access: campus 2015-01-31
Host Institution: UCF

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