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Title: Reactive sputter deposition of lithium phosphorus oxynitride thin films, a Li battery solid state electrolyte.
Creator: Mani, Prabhu Doss, Coffey, Kevin, Heinrich, Helge, Hickman, James, Sundaram, Kalpathy, University of Central Florida
Abstract / Description: Lithium phosphorus oxy-nitride (LiPON) thin films are widely studied and used as a thin film electrolyte for lithium ion battery applications. LiPON thin films may be prepared by many techniques, but RF sputter deposition is most frequently used and was investigated in this dissertation, in spite of its low deposition rate, because of it offers more reliable and controllable processing. This dissertation includes the methodologies of sputter deposition and materials characterization of the...
Show moreLithium phosphorus oxy-nitride (LiPON) thin films are widely studied and used as a thin film electrolyte for lithium ion battery applications. LiPON thin films may be prepared by many techniques, but RF sputter deposition is most frequently used and was investigated in this dissertation, in spite of its low deposition rate, because of it offers more reliable and controllable processing. This dissertation includes the methodologies of sputter deposition and materials characterization of the LiPON thin film electrolytes.The LiPON thin films were deposited under varying conditions of process gas, substrate bias, and deposition temperature. To understand the variations in ionic conductivity observed, the films were extensively characterized to examine structural and compositional differences, including examination by x-ray photoelectron spectroscopy (XPS), inductively coupled plasma optical emission spectroscopy (ICP/OES), and spectroscopic ellipsometry. In addition, film density, and the intrinsic stress of the deposited films were also studied.The highest ionic conductivity of 9.8 x 10-6 S/cm was obtained at elevated deposition temperature and is correlated to a reduced density of defects, as indicated from the optical characterization.
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Date Issued: 2015
Identifier: CFE0005835, ucf:50929
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005835

Title: Work Function Extraction of Indium Tin Oxide Used As Transparent Gate Electrode For MOSFET.
Creator: Nehate, Shraddha, Sundaram, Kalpathy, Kapoor, Vikram, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: Recent commercialization has peaked interest in transparent conducting oxides being implemented in display technology. Indium Tin Oxide (ITO) is a popular transparent conducting oxide which has been utilized as high work function electrode in liquid crystal displays, solar cells, gas sensors and heat reflecting films. Indium Tin Oxide films exhibit excellent transmission characteristics in the visible and infrared spectrum while maintaining high electrical conductivity. High work function...
Show moreRecent commercialization has peaked interest in transparent conducting oxides being implemented in display technology. Indium Tin Oxide (ITO) is a popular transparent conducting oxide which has been utilized as high work function electrode in liquid crystal displays, solar cells, gas sensors and heat reflecting films. Indium Tin Oxide films exhibit excellent transmission characteristics in the visible and infrared spectrum while maintaining high electrical conductivity. High work function electrodes are used to inject holes into organic materials. In majority applications the ITO work function has an impact on the device performance as it affects the energy barrier height at the hetero-junction interface. Hence, the work function of ITO is of critical importance.In this thesis, the work function of ITO is extracted successfully from a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device for the first time. Two MOSFET devices are fabricated using a four level mask under exact same conditions. Aluminum metal is used as a drain and source contact for both MOSFETs. One of the MOSFET has aluminum gate contact and transparent conducting ITO is used as gate contact for the second MOSFET. From the threshold voltage equation of both the fabricated MOSFETs, work function of ITO is extracted. Further optical transmission studies of ITO performed in the visible spectra are also reported in this study.
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Date Issued: 2016
Identifier: CFE0006364, ucf:51534
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006364

Title: Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation.
Creator: Mendoza Macias, Raul, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Fan, Deliang, University of Central Florida
Abstract / Description: Vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In...
Show moreVertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In addition, electrical parameters such as threshold voltage and charge balance are also examined. Increasing the superjunction doping in the drift region of VDMOS reduces the on-resistance by 26%, while maintaining the same breakdown voltage and threshold voltage compared to that of the conventional VDMOS power transistor with similar device design without using a superjunction.
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Date Issued: 2016
Identifier: CFE0006354, ucf:51525
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006354

Title: Three-Dimensional Simulation Study of Low Voltage ((<)100V) Superjunction Lateral DMOS power transistors.
Creator: Garcia, Jhonatan, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Fan, Deliang, University of Central Florida
Abstract / Description: A new revolutionary concept was presented two decades ago, known as (")semiconductor Superjunction (SJ) theory(") to enhance the trade-off relationship between speci?c on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was ?rst applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures,...
Show moreA new revolutionary concept was presented two decades ago, known as (")semiconductor Superjunction (SJ) theory(") to enhance the trade-off relationship between speci?c on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was ?rst applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures, principles and design techniques for discrete power MOSFETs. It also presents a simulation study of the application of these SJ concepts in the design of a Low Voltage SJ LDMOS transistor, using TCAD software. To make the device commercially feasible, this device design targets aggressive goals such as an off-state Breakdown Voltage of 60V with Rspof 20 miliohms per milimiter square. This study includes the analysis of the ?ow process for the fabrication of this transistor, using semiconductor technologies, and the simulation results, including Breakdown Voltage, on-state resistance, electric ?eld distribution among others simulation analysis.
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Date Issued: 2016
Identifier: CFE0006306, ucf:51600
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006306

Title: LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation.
Creator: Salih, Aiman, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Kapoor, Vikram, University of Central Florida
Abstract / Description: The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ...
Show moreThe benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance (&)#215; gate charge) of 5.93 m?-nC.
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Date Issued: 2017
Identifier: CFE0006955, ucf:51673
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006955

Title: Investigation on electrical properties of RF sputtered deposited BCN thin films.
Creator: Prakash, Adithya, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Lin, Mingjie, University of Central Florida
Abstract / Description: The ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated...
Show moreThe ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated circuit (ULSI) devices. In order to reduce the time delay, it is necessary to introduce a wiring metal with low resistivity and a high quality insulating film with a low dielectric constant which leads to a reduction of the wiring capacitance.Boron carbon nitride (BCN) films are prepared by reactive magnetron sputtering from a B(&)#172;4C target and deposited to make metal-insulator-metal (MIM) sandwich structures using aluminum as the top and bottom electrodes. BCN films are deposited at various N2/Ar gas flow ratios, substrate temperatures and process pressures. The electrical characterization of the MIM devices includes capacitance vs. voltage (C-V), current vs voltage, and breakdown voltage characteristics. The above characterizations are performed as a function of deposition parameters.
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Date Issued: 2013
Identifier: CFE0004912, ucf:49625
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004912

Title: Transparent Oxide Semiconductor Gate based MOSFETs for Sensor Applications.
Creator: Saikumar, Ashwin Kumar, Sundaram, Kalpathy, Wu, Thomas, Kapoor, Vikram, University of Central Florida
Abstract / Description: Starting from small scale laboratories to the highly sophisticated industrial facilities, monitoring and control forms the most integral part. In order to perform this continuous monitoring we require an interface, that would operate between the system and its processing conditions and in turn which facilitates us to act accordingly. This interface is called as a sensor. There are various types of sensors available which have wide range of functionality in various different fields.The use of...
Show moreStarting from small scale laboratories to the highly sophisticated industrial facilities, monitoring and control forms the most integral part. In order to perform this continuous monitoring we require an interface, that would operate between the system and its processing conditions and in turn which facilitates us to act accordingly. This interface is called as a sensor. There are various types of sensors available which have wide range of functionality in various different fields.The use of transparent conducting oxide (TCO) in the field of sensor applications has increasedand has been the subject of extensive research. Good electrical properties, good optical properties, wide band gap, portability, easy processing, and low cost has led to the extensive research on TCO for sensor applications.For this research purpose two specific types of sensor applications namely, light sensing and humidity sensing were considered. For this purpose, two sets of metal-oxide-semiconductor field effect transistors (MOSFET) with one set having transparent aluminum doped zinc oxide and the other having indium tin oxide respectively as their gate metal was fabricated. The MOSFETs werefabricated using a four level mask and tested.
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Date Issued: 2014
Identifier: CFE0005547, ucf:50297
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005547

Title: Lithographic Vertical-Cavity Surface-Emitting Lasers.
Creator: Zhao, Guowei, Deppe, Dennis, Likamwa, Patrick, Fathpour, Sasan, Sundaram, Kalpathy, University of Central Florida
Abstract / Description: Remarkable improvements in vertical-cavity surface-emitting lasers (VCSELs) have been made by the introduction of mode- and current-confining oxide optical aperture now used commercially. However, the oxide aperture blocks heat flow inside the device, causing a larger thermal resistance, and the internal strain caused by the oxide can degrade device reliability, also the diffusion process used for the oxide formation can limit device uniformity and scalability.Oxide-free lithographic VCSELs...
Show moreRemarkable improvements in vertical-cavity surface-emitting lasers (VCSELs) have been made by the introduction of mode- and current-confining oxide optical aperture now used commercially. However, the oxide aperture blocks heat flow inside the device, causing a larger thermal resistance, and the internal strain caused by the oxide can degrade device reliability, also the diffusion process used for the oxide formation can limit device uniformity and scalability.Oxide-free lithographic VCSELs are introduced to overcome these device limitations, with both the mode and current confined within the lithographically defined intracavity mesa, scaling and mass production of small size device could be possible. The 3 ?m diameter lithographic VCSEL shows a threshold current of 260 ?A, differential quantum efficiency of 60% and maximum output power density of 65 kW/cm2, and shows single-mode single-polarization operation with side-mode-suppression-ratio over 25 dB at output power up to 1 mW. The device also shows reliable operation during 1000 hours stress test with high injection current density of 142 kA/cm2. The lithographic VCSELs have much lower thermal resistance than oxide-confined VCSELs due to elimination of the oxide aperture. The improved thermal property allows the device to have wide operating temperature range of up to 190 (&)deg;C heat sink temperature, high output power density especially in small device, high rollover current density and high rollover cavity temperature. Research is still underway to reduce the operating voltage of lithographic VCSELs for high wall plug efficiency, and the voltage of 6 (&)#181;m device at injection current density of 10 kA/cm2 is reduces to 1.83 V with optimized mesa and DBR mirror structure. The lithographic VCSELS are promising to become the next generation VCSEL technology.
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Date Issued: 2012
Identifier: CFE0004634, ucf:49912
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004634

Title: Investigation of different dielectric materials as gate insulator for MOSFETs.
Creator: Oswal, Ritika, Sundaram, Kalpathy, Kapoor, Vikram, Wahid, Parveen, University of Central Florida
Abstract / Description: The scaling of semiconductor transistors has led to a decrease in thickness of the silicon dioxide layer used as gate dielectric. The thickness of the silicon dioxide layer is reduced to increase the gate capacitance, thus increasing the drain current. If the thickness of the gate dielectric decreases below 2nm, the leakage current due to the tunneling increases drastically. Hence it is necessary to replace the gate dielectric, silicon dioxide, with a physically thicker oxide layer of high-k...
Show moreThe scaling of semiconductor transistors has led to a decrease in thickness of the silicon dioxide layer used as gate dielectric. The thickness of the silicon dioxide layer is reduced to increase the gate capacitance, thus increasing the drain current. If the thickness of the gate dielectric decreases below 2nm, the leakage current due to the tunneling increases drastically. Hence it is necessary to replace the gate dielectric, silicon dioxide, with a physically thicker oxide layer of high-k materials like Hafnium oxide and Titanium oxide. High-k dielectric materials allow the capacitance to increase without a huge leakage current. Hafnium oxide and Titanium oxide films are deposited by reactive magnetron sputtering from Hafnium and Titanium targets respectively. These oxide layers are used to create metal-insulator-metal (MIM) structures using aluminum as the top and bottom electrodes. The films are deposited at various O2/Ar gas flow ratios, substrate temperatures, and process pressures. After attaining an exact recipe for these oxide layers that exhibit the desired parameters, MOS capacitors are fabricated with n-Si and p-Si substrates having aluminum electrodes at the top and bottom of each. Comparing the parameters of Hafnium oxide- and Titanium oxide- based MOS capacitors, MOSFET devices are designed with Hafnium oxide as gate dielectric.
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Date Issued: 2014
Identifier: CFE0005226, ucf:50612
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005226

Title: Cascaded Digital Refinement for Intrinsic Evolvable Hardware.
Creator: Thangavel, Vignesh, DeMara, Ronald, Sundaram, Kalpathy, Song, Zixia, University of Central Florida
Abstract / Description: Intrinsic evolution of reconfigurable hardware is sought to solve computational problems using the intrinsic processing behavior of System-on-Chip (SoC) platforms. SoC devices combine capabilities of analog and digital embedded components within a reconfigurable fabric under software control. A new technique is developed for these fabrics that leverages the digital resources' enhanced accuracy and signal refinement capability to improve circuit performance of the analog resources' which are...
Show moreIntrinsic evolution of reconfigurable hardware is sought to solve computational problems using the intrinsic processing behavior of System-on-Chip (SoC) platforms. SoC devices combine capabilities of analog and digital embedded components within a reconfigurable fabric under software control. A new technique is developed for these fabrics that leverages the digital resources' enhanced accuracy and signal refinement capability to improve circuit performance of the analog resources' which are providing low power processing and high computation rates. In particular, Differential Digital Correction (DDC) is developed utilizing an error metric computed from the evolved analog circuit to reconfigure the digital fabric thereby enhancing precision of analog computations. The approach developed herein, Cascaded Digital Refinement (CaDR), explores a multi-level strategy of utilizing DDC for refining intrinsic evolution of analog computational circuits to construct building blocks, known as Constituent Functional Blocks (CFBs). The CFBs are developed in a cascaded sequence followed by digital evolution of higher-level control of these CFBs to build the final solution for the larger circuit at-hand. One such platform, Cypress PSoC-5LP was utilized to realize solutions to ordinary differential equations by first evolving various powers of the independent variable followed by that of their combinations to emulate mathematical series-based solutions for the desired range of values. This is shown to enhance accuracy and precision while incurring lower computational energy and time overheads. The fitness function for each CFB being evolved is different from the fitness function that is defined for the overall problem.
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Date Issued: 2015
Identifier: CFE0005723, ucf:50123
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005723

Title: Spray_Deposited Titanium-Oxide Films For Infrared Optics, Photonics, And Solar Cell Applications.
Creator: Alhasan, Sarmad, Peale, Robert, Sundaram, Kalpathy, Mikhael, Wasfy, Abdolvand, Reza, Kar, Aravinda, University of Central Florida
Abstract / Description: Self-assembled TiO2 foam-like films, were grown by the water based Streaming Process for ElectrodelessElectrochemical Deposition (SPEED). The morphology of the 1 m thick films consistsof a tangled ropy structure with individual strands of 200 nm diameter and open pores of 0.1to 3 micron dimensions. Such films are advantageous for proposed perovskite solar cell comprisingCH3NH3PbI3 absorber with additional inorganic films as contact and conduction layers,all deposited by SPEED. Lateral film...
Show moreSelf-assembled TiO2 foam-like films, were grown by the water based Streaming Process for ElectrodelessElectrochemical Deposition (SPEED). The morphology of the 1 m thick films consistsof a tangled ropy structure with individual strands of 200 nm diameter and open pores of 0.1to 3 micron dimensions. Such films are advantageous for proposed perovskite solar cell comprisingCH3NH3PbI3 absorber with additional inorganic films as contact and conduction layers,all deposited by SPEED. Lateral film resistivity is in the range 20 - 200 k-cm, increasing withgrowth temperature, while sheet resistance is in the range 2 ?? 20 108 /Sq. Xray diffractionconfirms presence of TiO2 crystals of orthorhombic class (Brookite). UV-vis spectroscopy showshigh transmission below the expected 3.2 eV TiO2 bandgap. Transmittance increases with growthtemperature. This is a Ropy TiO2 thin film.We also prepared a Smooth TiO2 thin film. Self-assembled TiO2 film deposited by aqueous-spraydeposition was investigated to evaluate morphology, crystalline phase, and infrared optical constants.The Anatase nano-crystalline film had 10 nm characteristic surface roughness sparselypunctuated by defects of not more than 200 nm amplitude. The film is highly transparent throughoutthe visible to wavelengths of 12 m. The indirect band gap was determined to be 3.2 eV. Importantfor long-wave infrared applications is that dispersion in this region is weak compared with themore commonly used dielectic SiO2 for planar structures. The low-cost, large-area, atmosphericpressure,chemical spray deposition method allows conformal fabrication on flexible substrates forlong-wave infrared photonics.For comparison TiO2 films deposited by electron-beam evaporation were evaluated to determinemorphology, crystalline phase, and optical transparency.The evaporated TiO2 film was amorphous but crystallized into Anatase phase after annealing.Such film is attractive as electron conductor of unprecedented thinness and flexibility for proposedperovskite solar cell comprising CH3NH3PbI3 absorber with additional inorganic films as contactand conduction layers. The spray deposition method would allow conformal solar cell fabricationon flexible substrates for wearable power generation. Band gap of Evaporated TiO2 film is 4.0 eV.We prepared BaTiO3 thin film to know infrared pyroelectric response.Self-assembled nano-crystalline BaTiO3 films on stainless steel foil substrates, were grown by thewater based Streaming Process for Electrodeless Electrochemical Deposition (SPEED). SPEED isan aqueous process that deposits self-assembled nano-crystalline inorganic thin films over largeareas, without a vacuum, providing a scalable and manufacturing friendly process to fabricatedurable films. The morphology of the 1m thick films comprises single crystals of micron dimensionsimbedded in a matrix of nanocrystals. XRD confirms presence of BaTiO3 crystals ofhexagonal phase for samples annealed at 500C. Subsequent annealing at 600C transforms thefilm to the cubic phase. Potential applications include dielectric layers, capacitors, waveguides,ferroelectric RAM, pyroelectric infrared detectors, and phosphors. Characterization of infraredpyroelectric response at 10m wavelength shows an initially good sensitivity that reversibly decaysover a period of days due to water vapor absorption. A short-lived photo-response due topoling of the hydrated sample is also observed. We studied BaTiO3 to know hysteresis loop.Pyroelectric photoresponse of aqueous spray deposited thin films containing BaTiO3 nano-crystalsis reported. X-ray diffraction data indicate the presence of hexagonal BaTiO3 nano-crystals with20 nm crystalline domains in a matrix of some as yet unidentified nano-crystalline material.When the film is annealed at 600C, the X-ray pattern changes significantly and indicates a conversionto one of the non-hexagonal phases of BaTiO3 as well as a complete change in the matrix.With suitable amplifier, the measured photoresponse was 40V/W.Ferroelectric hysteresis on a film with significant presence of hexagonal BaTiO3 shows saturatedpolarization which is about 5-times smaller than for the bulk tetragonal phase.
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Date Issued: 2017
Identifier: CFE0006710, ucf:51899
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006710

Title: Semiconductor Design and Manufacturing Interplay to Achieve Higher Yields at Reduced Costs using SMART Techniques.
Creator: Oberai, Ankush Bharati, Yuan, Jiann-Shiun, Abdolvand, Reza, Georgiopoulos, Michael, Sundaram, Kalpathy, Reilly, Charles, University of Central Florida
Abstract / Description: Since the outset of IC Semiconductor market there has been a gap between its design and manufacturing communities. This gap continued to grow as the device geometries started to shrink and the manufacturing processes and tools got more complex. This gap lowered the manufacturing yield, leading to higher cost of ICs and delay in their time to market. It also impacted performance of the ICs, impacting the overall functionality of the systems they were integrated in. However, in the recent years...
Show moreSince the outset of IC Semiconductor market there has been a gap between its design and manufacturing communities. This gap continued to grow as the device geometries started to shrink and the manufacturing processes and tools got more complex. This gap lowered the manufacturing yield, leading to higher cost of ICs and delay in their time to market. It also impacted performance of the ICs, impacting the overall functionality of the systems they were integrated in. However, in the recent years there have been major efforts to bridge the gap between design and manufacturing using software solutions by providing closer collaborations techniques between design and manufacturing communities. The root cause of this gap is inherited by the difference in the knowledge and skills required by the two communities. The IC design community is more microelectronics, electrical engineering and software driven whereas the IC manufacturing community is more driven by material science, mechanical engineering, physics and robotics. The cross training between the two is almost nonexistence and not even mandated. This gap is deemed to widen, with demand for more complex designs and miniaturization of electronic appliance-products. Growing need for MEMS, 3-D NANDS and IOTs are other drivers that could widen the gap between design and manufacturing. To bridge this gap, it is critical to have close loop solutions between design and manufacturing This could be achieved by SMART automation on both sides by using Artificial Intelligence, Machine Learning and Big Data algorithms. Lack of automation and predictive capabilities have even made the situation worse on the yield and total turnaround times. With the growing fabless and foundry business model, bridging the gap has become even more critical. Smart Manufacturing philosophy must be adapted to make this bridge possible. We need to understand the Fab-fabless collaboration requirements and the mechanism to bring design to the manufacturing floor for yield improvement. Additionally, design community must be educated with manufacturing process and tool knowledge, so they can design for improved manufacturability. This study will require understanding of elements impacting manufacturing on both ends of the design and manufacturing process. Additionally, we need to understand the process rules that need to be followed closely in the design phase. Best suited SMART automation techniques to bridge the gap need to be studied and analyzed for their effectiveness.
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Date Issued: 2018
Identifier: CFE0007351, ucf:52096
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007351

Title: DESIGN OF HIGH EFFICIENCY BRUSHLESS PERMANENT MAGNET MACHINES AND DRIVER SYSTEM.
Creator: He, Chengyuan, Wei, Lei, Sundaram, Kalpathy, Zhou, Qun, Jin, Yier, Zou, Shengli, University of Central Florida
Abstract / Description: The dissertation is concerned with the design of high-efficiency permanent magnet synchronous machinery and the control system. The dissertation first talks about the basic concept of the permanent magnet synchronous motor (PMSM) design and the mathematics design model of the advanced design method. The advantage of the design method is that it can increase the high load capacity at no cost of increasing the total machine size. After that, the control method of the PMSM and Permanent magnet...
Show moreThe dissertation is concerned with the design of high-efficiency permanent magnet synchronous machinery and the control system. The dissertation first talks about the basic concept of the permanent magnet synchronous motor (PMSM) design and the mathematics design model of the advanced design method. The advantage of the design method is that it can increase the high load capacity at no cost of increasing the total machine size. After that, the control method of the PMSM and Permanent magnet synchronous generator (PMSG) is introduced. The design, simulation, and test of a permanent magnet brushless DC (BLDC) motor for electric impact wrench and new mechanical structure are first presented based on the design method. Finite element analysis based on the Maxwell 2D is built to optimize the design and the control board is designed using Altium Designer. Both the motor and control board have been fabricated and tested to verify the design. The electrical and mechanical design are combined, and it provides an analytical IPMBLDC design method and an innovative and reasonable mechanical dynamical calculation method for the impact wrench system, which can be used in whole system design of other functional electric tools. A 2kw high-efficiency alternator system and its control board system are also designed, analyzed and fabricated applying to the truck auxiliary power unit (APU). The alternator system has two stages. The first stage is that the alternator three-phase outputs are connected to the three-phase active rectifier to get 48V DC. An advanced Sliding Mode Observer (SMO) is used to get an alternator position. The buck is used for the second stage to get 14V DC output. The whole system efficiency is much higher than the traditional system using induction motor.
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Date Issued: 2018
Identifier: CFE0007334, ucf:52135
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007334

Title: Programmable Low Loss Orthogonal Frequency Coded Surface Acoustic Wave Correlator Filters.
Creator: Smith, Marshall, Malocha, Donald, Weeks, Arthur, Sundaram, Kalpathy, Richie, Samuel, Youngquist, Robert, University of Central Florida
Abstract / Description: Simultaneous Transmit and Receive (STAR) communication is being developed as a means of improving spectral efficiency in wireless communication systems. If the obstacle of self-interference can be sufficiently overcome, it is possible to double the spectral efficiency of an equivalent time or frequency division duplexed system. Spread spectrum techniques can reduce self-interference by using orthogonal or pseudo-orthogonal codes to encode the transmit signal and decode the receive signal...
Show moreSimultaneous Transmit and Receive (STAR) communication is being developed as a means of improving spectral efficiency in wireless communication systems. If the obstacle of self-interference can be sufficiently overcome, it is possible to double the spectral efficiency of an equivalent time or frequency division duplexed system. Spread spectrum techniques can reduce self-interference by using orthogonal or pseudo-orthogonal codes to encode the transmit signal and decode the receive signal.Hardware correlator filters are developed for use with STAR radio systems using orthogonal frequency coded (OFC) surface acoustic wave (SAW) devices. OFC is a type of spread spectrum communication that can be implemented using SAW transducers to create a correlator filter, also known as a matched filter. OFC allows code division multiple access and processing gain, similar to other spread spectrum techniques, but is more well-suited to low loss inline SAW design due to the use of multiple orthogonal carriers.The development of low loss fixed code OFC SAW correlator filters is documented, including design criteria and multiple approaches that progressively reduce insertion loss. Using the results from progressive designs and experiments, a pair of correlator filters with matched codes are presented with approximately 6 dB insertion loss at 950 MHz.A second development focusing on OFC SAW correlator filters with programmable codes using RF switches is also described. The programmable correlators use a fixed OFC code with programmable binary phase shift keying (BPSK), and demonstrate positive results. The programmable correlators presented require less than 1 mW of DC power.
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Date Issued: 2018
Identifier: CFE0007768, ucf:52372
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007768

Title: Advanced Control Techniques for Efficiency and Power Density Improvement of a Three-Phase Microinverter.
Creator: Tayebi, Seyed Milad, Batarseh, Issa, Mikhael, Wasfy, Sundaram, Kalpathy, Sun, Wei, Kutkut, Nasser, University of Central Florida
Abstract / Description: Inverters are widely used in photovoltaic (PV) based power generation systems. Most of these systems have been based on medium to high power string inverters. Microinverters are gaining popularity over their string inverter counterparts in PV based power generation systems due to maximized energy harvesting, high system reliability, modularity, and simple installation. They can be deployed on commercial buildings, residential rooftops, electric poles, etc and have a huge potential market....
Show moreInverters are widely used in photovoltaic (PV) based power generation systems. Most of these systems have been based on medium to high power string inverters. Microinverters are gaining popularity over their string inverter counterparts in PV based power generation systems due to maximized energy harvesting, high system reliability, modularity, and simple installation. They can be deployed on commercial buildings, residential rooftops, electric poles, etc and have a huge potential market. Emerging trend in power electronics is to increase power density and efficiency while reducing cost. A powerful tool to achieve these objectives is the development of an advanced control system for power electronics. In low power applications such as solar microinverters, increasing the switching frequency can reduce the size of passive components resulting in higher power density. However, switching losses and electromagnetic interference (EMI) may increase as a consequence of higher switching frequency. Soft switching techniques have been proposed to overcome these issues. This dissertation presents several innovative control techniques which are used to increase efficiency and power density while reducing cost. Dynamic dead time optimization and dual zone modulation techniques have been proposed in this dissertation to significantly improve the microinverter efficiency. In dynamic dead time optimization technique, pulse width modulation (PWM) dead times are dynamically adjusted as a function of load current to minimize MOSFET body diode conduction time which reduces power dissipation. This control method also improves total harmonic distortion (THD) of the inverter output current. To further improve the microinverter efficiency, a dual-zone modulation has been proposed which introduces one more soft-switching transition and lower inductor peak current compared to the other boundary conduction mode (BCM) modulation methods.In addition, an advanced DC link voltage control has been proposed to increase the microinverter power density. This concept minimizes the storage capacitance by allowing greater voltage ripple on the DC link. Therefore, the microinverter reliability can be significantly increased by replacing electrolytic capacitors with film capacitors. These control techniques can be readily implemented on any inverter, motor controller, or switching power amplifier. Since there is no circuit modification involved in implementation of these control techniques and can be easily added to existing controller firmware, it will be very attractive to any potential licensees.
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Date Issued: 2017
Identifier: CFE0007136, ucf:52328
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007136

Title: Heterogeneous Reconfigurable Fabrics for In-circuit Training and Evaluation of Neuromorphic Architectures.
Creator: Mohammadizand, Ramtin, DeMara, Ronald, Lin, Mingjie, Sundaram, Kalpathy, Fan, Deliang, Wu, Annie, University of Central Florida
Abstract / Description: A heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over...
Show moreA heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over fabrics having LUTs constructed with either individual technology alone. Herein, a hierarchical top-down design approach is used to develop the HSC(&)#173; FPGA starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication paradigms. This facilitates a novel architectural approach to reduce leakage energy, minimize communication occurrence and energy cost by eliminating unnecessary data transfer, and support auto-tuning for resilience. Furthermore, HSC-FPGA enables new advantages of technology co-design which trades off alternative mappings between emerging devices and transistors at runtime by allowing dynamic remapping to adaptively leverage the intrinsic computing features of each device technology. HSC-FPGA offers a platform for fine-grained Logic-In-Memory architectures and runtime adaptive hardware.An orthogonal dimension of fabric heterogeneity is also non-determinism enabled by either low(&)#173; voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Herein, consider the probabilistic spin logic p-bit device as a fabric element comprising a crossbar(&)#173; structured weighted array. The programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array's weighted connections. Thus, the programmable weighted array forms a CLB-scale macro co-processing element with bitstream programmability. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n(&)#215; m1(&)#215;m2(&)#215;...(&)#215;mi weighted array as a configurable hardware circuit with an n-input layer followed by i?1 hidden layers. As neuromorphic architectures using post-CMOS devices increase in capability and network size, the utility and benefits of reconfigurable fabrics of neuromorphic modules can be anticipated to continue to accelerate.
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Date Issued: 2019
Identifier: CFE0007502, ucf:52643
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007502

Title: Automated Synthesis of Unconventional Computing Systems.
Creator: Hassen, Amad Ul, Jha, Sumit Kumar, Sundaram, Kalpathy, Fan, Deliang, Ewetz, Rickard, Rahman, Talat, University of Central Florida
Abstract / Description: Despite decades of advancements, modern computing systems which are based on the von Neumann architecture still carry its shortcomings. Moore's law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes. On the other hand, modern computational requirements, driven by machine learning, pattern recognition, artificial intelligence, data mining, and IoT, are growing...
Show moreDespite decades of advancements, modern computing systems which are based on the von Neumann architecture still carry its shortcomings. Moore's law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes. On the other hand, modern computational requirements, driven by machine learning, pattern recognition, artificial intelligence, data mining, and IoT, are growing at the fastest pace ever. By their inherent nature, these applications are particularly affected by communication-bottlenecks, because processing them requires a large number of simple operations involving data retrieval and storage. The need to address the problems associated with conventional computing systems at the fundamental level has given rise to several unconventional computing paradigms. In this dissertation, we have made advancements for automated syntheses of two types of unconventional computing paradigms: in-memory computing and stochastic computing. In-memory computing circumvents the problem of limited communication bandwidth by unifying processing and storage at the same physical locations. The advent of nanoelectronic devices in the last decade has made in-memory computing an energy-, area-, and cost-effective alternative to conventional computing. We have used Binary Decision Diagrams (BDDs) for in-memory computing on memristor crossbars. Specifically, we have used Free-BDDs, a special class of binary decision diagrams, for synthesizing crossbars for flow-based in-memory computing. Stochastic computing is a re-emerging discipline with several times smaller area/power requirements as compared to conventional computing systems. It is especially suited for fault-tolerant applications like image processing, artificial intelligence, pattern recognition, etc. We have proposed a decision procedures-based iterative algorithm to synthesize Linear Finite State Machines (LFSM) for stochastically computing non-linear functions such as polynomials, exponentials, and hyperbolic functions.
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Date Issued: 2019
Identifier: CFE0007648, ucf:52462
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007648

Title: Design, Simulation and Characterization of Novel Electrostatic Discharge Protection Devices and Circuits in Advanced Silicon Technologies.
Creator: Liang, Wei, Sundaram, Kalpathy, Fan, Deliang, Jin, Yier, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be...
Show moreElectrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be destroyed easily, so ESD protection solutions are essential to semiconductor industry.ESD protection design consists of on-chip and off-chip ESD protection design, and the research works in this dissertation are all conducted in on-chip level, which incorporate the ESD protection devices and circuits into the microchip, to provide with basic ESD protection from manufacturing to customer use. The basic idea of ESD protection design is to provide a path with low impedance which directs most of the ESD current to flow through itself instead of the core circuit, and the ESD protection path must be robust enough to make sure that it does not fail before the core circuit. In this way, proper design on protection devices and circuits should be considered carefully. To assist the understanding and design of ESD protection, the ESD event in real world has been classified into a few ESD model including Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM), etc. Some mainstream testing method and industry standard are also introduced, including Transmission Line Pulse (TLP), and IEC 61000-4-2. ESD protection devices including diode, Gate-Grounded N-type MOSFET (GGNMOS), Silicon Controlled Rectifier (SCR) are basic elements for ESD protection design. In this dissertation, the device characteristics in ESD event and their applications are introduced. From the perspective of the whole chip ESD protection design, the concept of circuit level ESD protection and the ESD clamps are also briefly introduced. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation is widely used in ESD protection design. In this dissertation, TCAD and SPICE simulation are carried out for a few times for both of pre-tapeout evaluation on characteristics of the proposed device and circuit and post-tapeout analysis on structure operating mechanism.Automotive electronics has been a popular subject in semiconductor industry, and due to the special requirement of the automotive applications like the capacitive pins, the ESD protection device used in such applications need to be specially designed. In this dissertation, a few SCRs without snapback are discussed in detail. To avoid core circuit damages caused the displacement current induced by the large snapback in conventional SCR, an eliminated/minimized snapback is preferred in a selection of the protection device. Two novel SCRs are proposed for High Voltage (HV), Medium Voltage (MV), and Low Voltage (LV) automotive ESD protection.The typical operating temperature for ICs is up to 125 (&)#186;C, however in automotive applications, the operating temperature may extend up to 850 (&)#186;C. In this way, the characteristics of the ESD protection device under the elevated temperatures will be an essential part to investigate for automotive ESD protection design. In this dissertation, the high temperature characteristics of ESD protection devices including diode and a few SCRs is measured and discussed in detail. TCAD simulation are also conducted to explain the underlying physical mechanism. This work provides with a useful insight and information to ESD protection design in high temperature applications.Besides the high temperature environment, ESD protection are also highly needed for electronics working in other extreme environment like the space. Space is an environment that contains kinds of radiation source and at the same time can generate abundant ESD. The ESD adhering to the space systems could be a potential threat to the space electronics. At the same time, the characteristics of the ESD protection part especially the basic protection device used in the space electronics could be influenced after the irradiation in the space. Therefore, the investigation of the radiation effects on ESD protection devices are necessary. In this dissertation, the total ionizing dose (TID) effects on ESD protection devices are investigated. The devices are irradiated with 1.5 MeV He+ and characterized with TLP tester. The pre- and post-irradiation characteristics are compared and the variation on key ESD parameters are analyzed and discussed. This work offers a useful insight on ESD devices' operation under TID and help with the device designing on ESD protection devices for space electronics.Single ESD protection devices are essential part constructing the ESD protection network, however the optimization on ESD clamp circuit design is also important on building an efficient whole chip ESD protection network. In this dissertation, the design and simulation of a novel voltage triggered ESD detection circuit are introduced. The voltage triggered ESD detection circuit is proposed in a 0.18 um CMOS technology. Comparing with the conventional RC based detection circuit, the proposed circuit realizes a higher triggering efficiency with a much smaller footprint, and is immune to false triggering under fast power-up events. The proposed circuit has a better sensitivity to ESD event and is more reliable in ESD protection applications.The leakage current has been a concern with the scaling down of the thickness of the gate oxide. Therefore, a proper design of the ESD clamp for power rail ESD protection need to be specially considered. In this dissertation, a design of a novel ESD clamp with low leakage current is analyzed. The proposed clamp realized a pretty low leakage current up to 12 nA, and has a smaller footprint than conventional design. It also has a long hold-on time under ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the operation of the proposed ESD clamp.
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Date Issued: 2017
Identifier: CFE0007126, ucf:52298
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007126

Title: Security of Autonomous Systems under Physical Attacks: With application to Self-Driving Cars.
Creator: Dutta, Raj, Jin, Yier, Sundaram, Kalpathy, DeMara, Ronald, Zhang, Shaojie, Zhang, Teng, University of Central Florida
Abstract / Description: The drive to achieve trustworthy autonomous cyber-physical systems (CPS), which can attain goals independently in the presence of significant uncertainties and for long periods of time without any human intervention, has always been enticing. Significant progress has been made in the avenues of both software and hardware for fulfilling these objectives. However, technological challenges still exist and particularly in terms of decision making under uncertainty. In an autonomous system,...
Show moreThe drive to achieve trustworthy autonomous cyber-physical systems (CPS), which can attain goals independently in the presence of significant uncertainties and for long periods of time without any human intervention, has always been enticing. Significant progress has been made in the avenues of both software and hardware for fulfilling these objectives. However, technological challenges still exist and particularly in terms of decision making under uncertainty. In an autonomous system, uncertainties can arise from the operating environment, adversarial attacks, and from within the system. As a result of these concerns, human-beings lack trust in these systems and hesitate to use them for day-to-day use.In this dissertation, we develop algorithms to enhance trust by mitigating physical attacks targeting the integrity and security of sensing units of autonomous CPS. The sensors of these systems are responsible for gathering data of the physical processes. Lack of measures for securing their information can enable malicious attackers to cause life-threatening situations. This serves as a motivation for developing attack resilient solutions.Among various security solutions, attention has been recently paid toward developing system-level countermeasures for CPS whose sensor measurements are corrupted by an attacker. Our methods are along this direction as we develop an active and multiple passive algorithm to detect the attack and minimize its effect on the internal state estimates of the system. In the active approach, we leverage a challenge authentication technique for detection of two types of attacks: The Denial of Service (DoS) and the delay injection on active sensors of the systems. Furthermore, we develop a recursive least square estimator for recovery of system from attacks. The majority of the dissertation focuses on designing passive approaches for sensor attacks. In the first method, we focus on a linear stochastic system with multiple sensors, where measurements are fused in a central unit to estimate the state of the CPS. By leveraging Bayesian interpretation of the Kalman filter and combining it with the Chi-Squared detector, we recursively estimate states within an error bound and detect the DoS and False Data Injection attacks. We also analyze the asymptotic performance of the estimator and provide conditions for resilience of the state estimate.Next, we propose a novel distributed estimator based on l1 norm optimization, which could recursively estimate states within an error bound without restricting the number of agents of the distributed system that can be compromised. We also extend this estimator to a vehicle platoon scenario which is subjected to sparse attacks. Furthermore, we analyze the resiliency and asymptotic properties of both the estimators. Finally, at the end of the dissertation, we make an initial effort to formally verify the control system of the autonomous CPS using the statistical model checking method. It is done to ensure that a real-time and resource constrained system such as a self-driving car, with controllers and security solutions, adheres to strict timing constrains.
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Date Issued: 2018
Identifier: CFE0007174, ucf:52253
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007174

Title: Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies.
Creator: Dong, Aihua, Sundaram, Kalpathy, Fan, Deliang, Gong, Xun, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to...
Show moreElectrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to FinFET technology requires more robust ESD protection however the large parasitic capacitance of ESD protection cell is problematic in high-speed interface design. To reduce the parasitic capacitance, a dual diode silicon controlled rectifier (DD-SCR) is presented in this dissertation. This design can exhibit good trade-offs between ESD robustness and parasitic capacitance characteristics. Besides, different bounding materials lead to performance variations in DD-SCRs are compared. Radio frequency (RF) technology is also demanded low capacitance ESD protection. To address this concern, a ?-network is presented, providing robust ESD protection for 10-60 GHz RF circuit. Like a low pass ? filter, the network can reflect high frequency RF signals and transmit low frequency ESD pulses. Given proper inductor value, networks can work as robust ESD solutions at a certain Giga Hertz frequency range, making this design suitable for broad band protection in RF input/outputs (I/Os). To increase the holding voltage and reduce snapback, a resistor assist triggering heterogeneous stacking structure is presented in this dissertation, which can increase the holding voltage and also keep the trigger voltage nearly as same as a single SCR device.
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Date Issued: 2018
Identifier: CFE0007172, ucf:52251
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007172

ESD (3)	+ -
MOSFET (3)	+ -
XPS (3)	+ -
2D materials (2)	+ -
BST (2)	+ -

Cryogenic (2)	+ -
Electrostatic Discharge (2)	+ -
LDMOS (2)	+ -
MEMS (2)	+ -
Optimization (2)	+ -
PMSM (2)	+ -
Piezoelectric (2)	+ -
Power MOSFET (2)	+ -
Power Semiconductor (2)	+ -
RF (2)	+ -
Reliability (2)	+ -
Resonator (2)	+ -
Sputtering (2)	+ -
Superjunction (2)	+ -
TCAD (2)	+ -
Temperature (2)	+ -
Thin Films (2)	+ -
electromagnetic compatibility (2)	+ -
low-k materials (2)	+ -
metrology (2)	+ -
photovoltaic (2)	+ -
power amplifier (2)	+ -
thin film (2)	+ -
03/30/2018 (1)	+ -
ASCII (1)	+ -

University of Central Florida (73)	+ -
Sundaram, Kalpathy (71)	+ -
Yuan, Jiann-Shiun (25)	+ -
Abdolvand, Reza (10)	+ -
Gong, Xun (9)	+ -

Kapoor, Vikram (9)	+ -
Fan, Deliang (7)	+ -
Wei, Lei (7)	+ -
Jin, Yier (6)	+ -
Wahid, Parveen (6)	+ -
Chow, Lee (5)	+ -
Chow, Louis (5)	+ -
Malocha, Donald (5)	+ -
Salcedo, Javier (5)	+ -
Wu, Xinzhang (5)	+ -
Batarseh, Issa (4)	+ -
DeMara, Ronald (4)	+ -
Kar, Aravinda (4)	+ -
Schoenfeld, Winston (4)	+ -
Shen, Zheng (4)	+ -
Cho, Hyoung Jin (3)	+ -
Coffey, Kevin (3)	+ -
Fathpour, Sasan (3)	+ -
Lin, Mingjie (3)	+ -
Richie, Samuel (3)	+ -
Roy, Tania (3)	+ -
Atia, George (2)	+ -
Davis, Kristopher (2)	+ -
Heinrich, Helge (2)	+ -
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