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Title: Hole selective tunneling oxide applications with insight into sophisticated characterization techniques.
Creator: Ogutman, Nizamettin Kortan, Schoenfeld, Winston, Sundaram, Kalpathy, Batarseh, Issa, Davis, Kristopher, Dogariu, Aristide, University of Central Florida
Abstract / Description: Tunneling metal oxide layers combined with industrially applicable novel cleaning methods can boost the current efficiency limit, which corresponds to approximately %22 in production, of crystalline silicon (c-Si) solar cells. Within the scope of this dissertation, extremely thin tunneling layers (1-3nm) of aluminum oxide is studied in conjunction with the development of wet cleaning procedures that are feasible in production lines currently exist today. These tunneling stacks are deployed to...
Show moreTunneling metal oxide layers combined with industrially applicable novel cleaning methods can boost the current efficiency limit, which corresponds to approximately %22 in production, of crystalline silicon (c-Si) solar cells. Within the scope of this dissertation, extremely thin tunneling layers (1-3nm) of aluminum oxide is studied in conjunction with the development of wet cleaning procedures that are feasible in production lines currently exist today. These tunneling stacks are deployed to serve as exceptional surface passivation layers due to the inherent built-in charge provided by aluminum oxide. This capability is further strengthened by the introduction of extremely well controlled wet chemical oxide which not only saturates the dangling bonds at the interface but also enables conformal growth of the aforementioned tunneling oxide layers. Therefore, the interplay between aluminum oxide thickness, which effects the passivation quality tremendously, and carrier extraction capability (contact resistance) is also taken into account by the choice of ultimate boron doping profile and the optimization of the cleaning procedure. The resulting hole collecting surface passivation stack applied on doped surfaces provided record values of recombination current densities, with highly applicable contact resistivity values, enabling one-dimensional carrier transport. This dissertation is also concerned with spatially resolved characterization methods of such industrial c-Si solar cells given the importance of defects that can exist in these large area devices. Analytical image processing algorithms pertaining to biased-photoluminescence (PL) measurements are conducted to portray 2D maps of physical significant devices parameters such as dark saturation current density and efficiency. Finally, Fourier analysis is added into the analysis of raw PL images to pick up only the defected regions of the cells.
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Date Issued: 2018
Identifier: CFE0007069, ucf:51980
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007069

Title: Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions.
Creator: Li, Hang, Sundaram, Kalpathy, Batarseh, Issa, Fan, Deliang, Gong, Xun, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A...
Show moreElectrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A compact model is developed to predict thermal failure with circuit simulators. Instead of considering the detailed failure mechanisms, a failure temperature is introduced to indicate device failure. The developed model is implemented by a multiple-stage thermal network.P-N junction is the fundamental structure for ESD protection devices. An enhanced diode model is proposed and is used to simulate the device behaviors for ESD events. The model includes all physical effects for ESD conditions, which are voltage overshoot, self-heating effect, velocity saturation and thermal failure. The proposed model not only can fit the I-V and transient characteristics, but also can predict failure for different pulses.Safe Operating Area (SOA) is an important factor to evaluate the LDMOS performance. The transient SOA boundary is considered as power-defined. By placing the failure monitor under certain conditions, the developed modeling methodology can predict the boundary of transient SOA for any short pulse stress conditions. No matter failure happens before or after snapback phenomenon.Weibull distribution is popular to evaluate the dielectric lifetime for CVS. By using the transformative version of power law, the pulsing stresses are converted into CVS, and TDDB under ESD conditions for SiN MIMCAPs is analyzed. The thickness dependency and area independency of capacitor breakdown voltage is observed, which can be explained by the constant ?E model instead of conventional percolation model.
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Date Issued: 2019
Identifier: CFE0007670, ucf:52512
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007670

Title: Design and Implementation of Silicon-Based MEMS Resonators for Application in Ultra Stable High Frequency Oscillators.
Creator: Shahraini, Sarah, Abdolvand, Reza, Gong, Xun, Sundaram, Kalpathy, Kapoor, Vikram, Rajaraman, Swaminathan, University of Central Florida
Abstract / Description: The focus of this work is to design and implement resonators for ultra-stable high-frequency ((>)100MHz) silicon-based MEMS oscillators. Specifically, two novel types of resonators are introduced that push the performance of silicon-based MEMS resonators to new limits. Thin film Piezoelectric-on-Silicon (TPoS) resonators have been shown to be suitable for oscillator applications due to their combined high quality factor, coupling efficiency, power handling and doping-dependent temperature...
Show moreThe focus of this work is to design and implement resonators for ultra-stable high-frequency ((>)100MHz) silicon-based MEMS oscillators. Specifically, two novel types of resonators are introduced that push the performance of silicon-based MEMS resonators to new limits. Thin film Piezoelectric-on-Silicon (TPoS) resonators have been shown to be suitable for oscillator applications due to their combined high quality factor, coupling efficiency, power handling and doping-dependent temperature-frequency behavior. This thesis is an attempt to utilize the TPoS platform and optimize it for extremely stable high-frequency oscillator applications.To achieve the said objective, two main research venues are explored. Firstly, quality factor is systematically studied and anisotropy of single crystalline silicon (SCS) is exploited to enable high-quality factor side-supported radial-mode (aka breathing mode) TPoS disc resonators through minimization of anchor-loss. It is then experimentally demonstrated that in TPoS disc resonators with tethers aligned to [100], unloaded quality factor improves from ~450 for the second harmonic mode at 43 MHz to ~11,500 for the eighth harmonic mode at 196 MHz. Secondly, thickness quasi-Lam(&)#233; modes are studied and demonstrated in TPoS resonators for the first time. It is shown that thickness quasi-Lam(&)#233; modes (TQLM) could be efficiently excited in silicon with very high quality factor (Q). A quality factor of 23.2 k is measured in vacuum at 185 MHz for a fundamental TQLM-TPoS resonators designed within a circular acoustic isolation frame. Quality factor of 12.6 k and 6 k are also measured for the second- and third- harmonic TQLM TPoS resonators at 366 MHz and 555 MHz respectively. Turn-over temperatures between 40 (&)deg;C to 125 (&)deg;C are also designed and measured for TQLM TPoS resonators fabricated on degenerately N-doped silicon substrates. The reported extremely high quality factor, very low motional resistance, and tunable turn-over temperatures (>)80 (&)#186;C make these resonators a great candidate for ultra-stable oven-controlled high-frequency MEMS oscillators.
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Date Issued: 2019
Identifier: CFE0007861, ucf:52775
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007861

Title: GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs.
Creator: Binder, Andrew, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Roy, Tania, Kapoor, Vikram, Chow, Lee, University of Central Florida
Abstract / Description: GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is...
Show moreGaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ((<) 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition.
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Date Issued: 2019
Identifier: CFE0007885, ucf:52786
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007885

Title: Design, Characterization and Analysis of Electrostatic Discharge (ESD) Protection Solutions in Emerging and Modern Technologies.
Creator: Liu, Wen, Liou, Juin, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Chen, Quanfang, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and...
Show moreElectrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal(-)oxide(-)semiconductor (CMOS) technologies.The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diode-triggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end.
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Date Issued: 2012
Identifier: CFE0004571, ucf:49199
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004571

Title: STUDY OF DESIGN FOR RELIABILITY OF RF AND ANALOG CIRCUITS.
Creator: Tang, Hongxia, Yuan, Jiann-Shiun, Wu, Xinzhang, Sundaram, Kalpathy, Chow, Lee, University of Central Florida
Abstract / Description: Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design.An adaptive gate-source biasing...
Show moreDue to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design.An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point.A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 (&)#181;m mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators.A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO.A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.
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Date Issued: 2012
Identifier: CFE0004223, ucf:49000
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004223

Title: Characterization, Morphology, Oxidation, and Recession of Silicon Nanowires Grown by Electroless Process.
Creator: Mertens, Robert, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Chow, Louis, Wahid, Parveen, Blair, Richard, University of Central Florida
Abstract / Description: This dissertation presents heretofore undiscovered properties of Silicon Nanowires (SiNWs) grown by electroless process and presents mathematical solutions to the special problems of the oxidation and diffusion of dopants for SiNWs. Also presented here is a mathematical description of morphology of oxidized SiNWs. This dissertation is comprised of several discussions relating to SiNWs growth, oxidation, morphology and doping.In here is presented work derived from a long-term study of SiNWs....
Show moreThis dissertation presents heretofore undiscovered properties of Silicon Nanowires (SiNWs) grown by electroless process and presents mathematical solutions to the special problems of the oxidation and diffusion of dopants for SiNWs. Also presented here is a mathematical description of morphology of oxidized SiNWs. This dissertation is comprised of several discussions relating to SiNWs growth, oxidation, morphology and doping.In here is presented work derived from a long-term study of SiNWs. Several important aspects of SiNWs were investigated and the results published in journals and conference papers. The recession of SiNWs was heretofore unreported by other research groups. In our investigations, this began as a question, (")How far into the substrate does the etching process go when this method is used to make SiNWs?(") Our investigations showed that recession did take place, was controllable and that a number of variables were responsible. The growth mechanism of SiNWs grown by electroless process is discussed at length. The relation of exposed area to volume of solution is shown, derived from experimentation. A relation of Silver used to Si removed is presented, derived from experimentation. The agglomeration of SiNWs grown by the electroless process is presented.The oxidation of SiNWs is a subject of interest to many groups, although most other groups work with SiNWs grown by the VLS process, which is more difficult, time-consuming and expensive to do. The oxidation of planar Silicon (Si) is still a subject of study, even today, after many years of working with and refining our formulae, because of the changing needs of this science and industry. SiNWs oxidation formulae are more complicated than those for planar Si, partly because of their morphology and partly because of their scale. While planar Si only presents one orientation for oxidation, SiNWs present a range of orientations, usually everything between (<)100(>) and (<)110(>) ( the (<)111(>) orientation is usually not presented during oxidation). This complicates the post-oxidation morphology to the extent that, subsequent to oxidation, SiNWs are more rectangular than cylindrical in shape. After etching to remove an oxidation layer from the SiNWs, the rectangular shape shifts 90(&)deg; in orientation.In traditional oxidation, the Deal-Grove formulae are used, but when the oxidation must take place in very small layers, such as with nanoscale devices, the Massoud formulae have to be used. However, even with Massoud, these formulae are not as good because of the morphology. Deal-Grove and Massoud formulae are intended for use with planar Si. We present some formulae that show the change in shape of SiNWs during oxidation, due to their morphology.The diffusion of dopants in SiNWs is a subject few research groups have taken up. Most of the groups who have, use SiNWs grown by the VLS method to make measurements and report findings. In order to measure the diffusion of dopants in SiNWs, a controllable diameter is needed. There are a number of ways to measure diffusion in SiNWs, but none of the ones used so far apply well to SiNWs grown by electroless process. Usually these groups present some mathematical formulae to predict diffusion in SiNWs, but these seem to lack mathematical rigor. Diffusion is a process that is best understood using Fick's Laws, which are applied to the problem of SiNWs in this dissertation.Diffusion is a science with a long history, going back at least 150 years. There are many formulae that can be used in the most common diffusion processes, but the processes involved with the diffusion of dopants in SiNWs is more complex than the simple diffusion processes that are fairly well-understood. Diffusion doping of SiNWs is a multiphase process that is more complex, first because it is multiphase and second because the second step involves a multiplicity of diffusing elements, plus oxidation, which brings on the problems of moving boundaries.In this dissertation, we present solutions to these problems, and the two-step diffusion process for SiNWs.
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Date Issued: 2012
Identifier: CFE0004412, ucf:49366
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004412

Title: Optimization of Process Parameters for Faster Deposition of CuIn1-xGaxS2 and CuIn1-xGaxSe2-ySy Thin Film Solar Cells.
Creator: Kaul, Ashwani, Dhere, Neelkanth, Heinrich, Helge, Kar, Aravinda, Chow, Lee, Sundaram, Kalpathy, University of Central Florida
Abstract / Description: Thin film solar cells have the potential to be an important contributor to the world energy demand in the 21st century. Among all the thin film technologies, CuInGaSe2 (CIGS) thin film solar cells have achieved the highest efficiency. However, the high price of photovoltaic (PV) modules has been a major factor impeding their growth for terrestrial applications. Reduction in cost of PV modules can be realized by several ways including choosing scalable processes amenable to large area...
Show moreThin film solar cells have the potential to be an important contributor to the world energy demand in the 21st century. Among all the thin film technologies, CuInGaSe2 (CIGS) thin film solar cells have achieved the highest efficiency. However, the high price of photovoltaic (PV) modules has been a major factor impeding their growth for terrestrial applications. Reduction in cost of PV modules can be realized by several ways including choosing scalable processes amenable to large area deposition, reduction in the materials consumption of active layers, and attaining faster deposition rates suitable for in-line processing. Selenization-sulfurization of sputtered metallic Cu-In-Ga precursors is known to be more amenable to large area deposition. Sputter-deposited molybdenum thin film is commonly employed as a back contact layer for CIGS solar cells. However, there are several difficulties in fabricating an optimum back contact layer. It is known that molybdenum thin films deposited at higher sputtering power and lower gas pressure exhibit better electrical conductivity. However, such films exhibit poor adhesion to the soda-lime glass substrate. On the other hand, films deposited at lower discharge power and higher pressure although exhibit excellent adhesion show lower electrical conductivity. Therefore, a multilayer structure is normally used so as to get best from the two deposition regimes. A multi-pass processing is not desirable in high volume production because it prolongs total production time and correspondingly increases the manufacturing cost. In order to make manufacturing compliant with an in-line deposition, it is justifiable having fewer deposition sequences. Thorough analysis of pressure and power relationship of film properties deposited at various parameters has been carried out. It has been shown that it is possible to achieve a molybdenum back contact of desired properties in a single deposition pass by choosing the optimum deposition parameters. It is also shown that the film deposited in a single pass is actually a composite structure. CIGS solar cells have successfully been completed on the developed single layer back contact with National Renewable Energy Laboratory (NREL) certified device efficiencies (>)11%. The optimization of parameters has been carried out in such a way that the deposition of back contact and metallic precursors can be carried out in identical pressure conditions which is essential for in-line deposition without a need for load-lock. It is know that the presence of sodium plays a very critical role during the growth of CIGS absorber layer and is beneficial for the optimum device performance. The effect of sodium location during the growth of the absorber layer has been studied so as to optimize its quantity and location in order to get devices with improved performance. NREL certified devices with efficiencies (>)12% have been successfully completed.
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Date Issued: 2012
Identifier: CFE0004559, ucf:49261
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004559

Title: BST-Inspired Smart Flexible Electronics.
Creator: Shen, Ya, Gong, Xun, Wahid, Parveen, Sundaram, Kalpathy, Coffey, Kevin, University of Central Florida
Abstract / Description: The advances in modern communication systems have brought about devices with more functionality, better performance, smaller size, lighter weight and lower cost. Meanwhile, the requirement for newer devices has become more demanding than ever. Tunability and flexibility are both long-desired features. Tunable devices are 'smart' in the sense that they can adapt to the dynamic environment or varying user demand as well as correct the minor deviations due to manufacturing fluctuations,...
Show moreThe advances in modern communication systems have brought about devices with more functionality, better performance, smaller size, lighter weight and lower cost. Meanwhile, the requirement for newer devices has become more demanding than ever. Tunability and flexibility are both long-desired features. Tunable devices are 'smart' in the sense that they can adapt to the dynamic environment or varying user demand as well as correct the minor deviations due to manufacturing fluctuations, therefore making it possible to reduce system complexity and overall cost. It is also desired that electronics be flexible to provide conformability and portability.Previously, tunable devices on flexible substrates have been realized mainly by dicing and assembling. This approach is straightforward and easy to carry out. However, it will become a (")mission impossible(") when it comes to assembling a large amount of rigid devices on a flexible substrate. Moreover, the operating frequency is often limited by the parasitic effect of the interconnection between the diced device and the rest of the circuit on the flexible substrate. A recent effort utilized a strain-sharing Si/SiGe/Si nanomembrane to transfer a device onto a flexible substrate. This approach works very well for silicon based devices with small dimensions, such as transistors and varactor diodes. Large-scale fabrication capability is still under investigation.A new transfer technique is proposed and studied in this research. Tunable BST (Barium Strontium Titanate) IDCs (inter-digital capacitors) are first fabricated on a silicon substrate. The devices are then transferred onto a flexible LCP (liquid crystalline polymer) substrate using wafer bonding of the silicon substrate to the LCP substrate, followed by silicon etching. This approach allows for monolithic fabrication so that the transferred devices can operate in millimeter wave frequency. The tunability, capacitance, Q factor and equivalent circuit are studied. The simulated and measured performances are compared. BST capacitors on LCP substrates are also compared with those on sapphire substrates to prove that this transfer process does not impair the performance.A primary study of a reflectarray antenna unit cell is also conducted for loss and phase swing performance. The BST thin film layout and bias line positions are studied in order to reduce the total loss. Transferring a full-size BST-based reflectarray antenna onto an LCP substrate is the ultimate goal, and this work is ongoing at the University of Central Florida (UCF).HFSS is used to simulate the devices and to prove the concept. All of the devices are fabricated in the clean room at UCF. Probe station measurements and waveguide measurements are performed on the capacitors and reflectarray antenna unit cells respectively.This work is the first comprehensive demonstration of this novel transfer technique.
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Date Issued: 2012
Identifier: CFE0004439, ucf:49339
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004439

Title: Wireless Power Transfer for Space Applications: System Design and Electromagnetic Compatibility Compliance of Radiated Emissions.
Creator: Vazquez Ramos, Gabriel, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Wu, Xinzhang, Soto Toro, Felix, University of Central Florida
Abstract / Description: This dissertation evaluates the possibility of wireless power transfer (WPT) systems for space applications, with an emphasis in launch vehicles (rockets). After performing literature review for WPT systems, it was identified that magnetic resonance provides the more suited set of characteristics for this application. Advanced analysis, simulation and testing were performed to magnetic resonance WPT systems to acquire system performance insight. This was accomplished by evaluating/varying...
Show moreThis dissertation evaluates the possibility of wireless power transfer (WPT) systems for space applications, with an emphasis in launch vehicles (rockets). After performing literature review for WPT systems, it was identified that magnetic resonance provides the more suited set of characteristics for this application. Advanced analysis, simulation and testing were performed to magnetic resonance WPT systems to acquire system performance insight. This was accomplished by evaluating/varying coupling configuration, load effects and magnetic element physical characteristics (i.e. wire material, loop radius, etc.). It was identified by analysis, circuit simulation and testing that the best coupling configuration for this application was series-series and series-shunt with Litz wire loop inductors. The main concern identified for the implementation of these systems for space applications was radiated emissions that could potentially generate electromagnetic interference (EMI). To address this EMI concern, we developed the Electromagnetic Compatibility Radiated Emissions Compliance Design Evaluation Approach for WPT Space Systems. This approach systematically allocates key analyses, simulations and tests procedures to predict WPT EMC compliance to NASA's EMC standard Mil-Std-461E/F. Three prototype/magnetic elements were successfully assessed by implementing the WPT EMC design approach. The electric fields intensity generated by the WPT prototypes/magnetic elements tested were: 30.02 dBuV/m, 28.90 dBuV/m and 82.13 dBuV/m (requirement limit: 140 dBuV/m). All three prototypes successfully transferred power wirelessly and successfully met the NASA EMC requirements.
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Date Issued: 2012
Identifier: CFE0004448, ucf:49344
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004448

Title: Nanoarchitectured Energy Storage Devices.
Creator: Yu, Zenan, Thomas, Jayan, Seal, Sudipta, Zhai, Lei, Fang, Jiyu, Sundaram, Kalpathy, University of Central Florida
Abstract / Description: Supercapacitors, the devices that connect the gap between batteries and conventional capacitors, have recently attracted significant attention due to their high specific capacitance, substantially enhanced power and energy densities, and extraordinary cycle life. In order to realize even better performance with supercapacitors, rejuvenated effort towards developing nanostructured electrodes is necessary. In this dissertation, several strategic directions of nanoarchitecturing the electrodes...
Show moreSupercapacitors, the devices that connect the gap between batteries and conventional capacitors, have recently attracted significant attention due to their high specific capacitance, substantially enhanced power and energy densities, and extraordinary cycle life. In order to realize even better performance with supercapacitors, rejuvenated effort towards developing nanostructured electrodes is necessary. In this dissertation, several strategic directions of nanoarchitecturing the electrodes to enhance the performance of supercapacitors are investigated. An introduction and background of supercapacitors, which includes motivation, classification and working principles, recent nanostructured electrode materials studies, and devices fabrication, are initially presented. A facile method, called Spin-on Nanoprinting (SNAP), to fabricate highly ordered manganese dioxide (MnO2) nanopillars is introduced. The SNAP method that is further modified to develop carbon nanoarray electrodes is also discussed. Subsequently, a template-free method to develop high aspect ratio copper oxide nanowhiskers on copper substrate is presented, which boosts the surface area by 1000 times compared to non-nanostructured copper substrate. Electrochemically deposited MnO2 on the nanostructured substrate provided a specific capacitance of about 1379 F g-1 which is very close to the theoretical value (~ 1400 F g-1) due to this efficient nanostructure design. In addition, a novel method to decorate metal nanoparticles on graphene aerogel, which considerably enhances the electronic conductivity and the corresponding specific capacitance, is demonstrated. Moreover, ferric oxide (Fe2O3) nanorods prepared by a simple hydrothermal method is discussed. Asymmetric devices assembled based on Fe2O3 nanorods and MnO2 nanowhiskers show excellent electrochemical properties. The devices not only display the capability to store energy but also transmit electricity through the inner copper core. These two functions are independent and do not interfere with each other. Finally, a summary of this dissertation as well as some potential future directions are presented.
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Date Issued: 2015
Identifier: CFE0006062, ucf:50995
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006062

Title: Predictive modeling for assessing the reliability of bypass diodes in Photovoltaic modules.
Creator: Shiradkar, Narendra, Sundaram, Kalpathy, Schoenfeld, Winston, Atia, George, Abdolvand, Reza, Xanthopoulos, Petros, University of Central Florida
Abstract / Description: Solar Photovoltaics (PV) is one of the most promising renewable energy technologies for mitigating the effect of climate change. Reliability of PV modules directly impacts the Levelized Cost of Energy (LCOE), which is a metric for cost competitiveness of any energy technology. Further reduction in LCOE of PV through assured long term reliability is necessary in order to facilitate widespread use of solar energy without the need for subsidies. This dissertation is focused on frameworks for...
Show moreSolar Photovoltaics (PV) is one of the most promising renewable energy technologies for mitigating the effect of climate change. Reliability of PV modules directly impacts the Levelized Cost of Energy (LCOE), which is a metric for cost competitiveness of any energy technology. Further reduction in LCOE of PV through assured long term reliability is necessary in order to facilitate widespread use of solar energy without the need for subsidies. This dissertation is focused on frameworks for assessing reliability of bypass diodes in PV modules. Bypass diodes are critical components in PV modules that provide protection against shading. Failure of bypass diode in short circuit results in reducing the PV module power by one third, while diode failure in open circuit leaves the module susceptible for extreme hotspot heating and potentially fire hazard. PV modules, along with the bypass diodes are expected to last at least 25 years in field. The various failure mechanisms in bypass diodes such as thermal runaway, high temperature forward bias operation and thermal cycling are discussed. Operation of bypass diode under shading is modeled and method for calculating the module I-V curve under any shading scenario is presented. Frameworks for estimating the diode temperature in field deployed modules based on Typical Meteorological Year (TMY) data are developed. Model for predicting the susceptibility of bypass diodes for thermal runaway is presented. Diode wear out due to High Temperature Forward Bias (HTFB) operation and Thermal Cycling (TC) is studied under custom designed accelerated tests. Overall, this dissertation is an effort towards estimating the lifetime of bypass diodes in field deployed modules, and therefore, reducing the uncertainty in long term reliability of PV modules.
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Date Issued: 2015
Identifier: CFE0006001, ucf:51023
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006001

Title: Design and characterization of system level electrostatic discharge (ESD) protection solutions.
Creator: Xi, Yunfeng, Liou, Juin, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between 'objects' to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits...
Show moreElectrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between 'objects' to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits across existing and emerging network infrastructures. This tendency is driving an expansion in data communication as well as industrial applications environment. To keep up with the interconnectivity expansion, the industry requires new devices to support more effectively high speed signals processing over long distances and be able to reliably operate in harsh and noisy environments. Electrical over-stress transients caused by ESD or switching of inductive loads can corrupt data transmission and damage bus transceivers unless effective measures are taken to address the impact of such high energy transient stress conditions. Today's industry specifications for integrated circuits require 1kV HBM on all pins, but selected pins with direct contact to the external environment must comply with levels as high as 8kV for IEC 61000-4-2 and ISO 10605 standards. The rapid evolution of the handheld and mobile device market segment, dramatic increase of electronic content in automotive products, and substantial progress in industrial and medical applications created a new need for on-chip protection against system level ESD stresses. This PhD work investigates the impact of system-level type of ESD stress on components. Firstly, correlation factors between different ESD pulse types for different BEOL metal line topologies have been studied to support system level on-chip ESD design. The component level (HMM, HBM and TLP on wafer) and system level (IEC gun contact on package) ESD stresses were correlated followed by extraction of correlation factors between the IEC/HMM and TLP, as well as the HBM and TLP supported by analytical approximation. The major conclusions were verified using the thermal coupled mixed-mode simulations analysis. Secondly, operation of NLDMOS-SCR devices under the HMM and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, while both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such a dependency has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40ns. In the last section, a new silicon-controlled rectifier (SCR) fabricated in a 30 V mixed-signal CDMOS (CMOS/DMOS) technology is presented. This device allows for robust EMI (electromagnetic interference) and ESD (electrostatic discharge) protection solution for high speed industrial interface applications operating in variable voltage swing range from -7V to +12V. This new SCR has reduced overshoot voltage and leakage current when electrically stressed under different pulse widths and temperatures. Analysis of the device physics is complemented via numerical TCAD mixed-mode simulations. A 200 x 200 (&)#181;m2 device designed in an annular configuration achieved (>) (&)#177; 8 kV IEC robustness by handling (>) (&)#177; 20 Amp of TLP current while clamping the voltage to (&)#177;3V within 2-nsec.
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Date Issued: 2016
Identifier: CFE0006199, ucf:51113
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006199

Title: Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event.
Creator: Miao, Meng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description: In this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide...
Show moreIn this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide-Semiconductor (DMOS) process are used for design of experiment. A multi-function test platform High Power Pulse Instrument (HPPI) is used for ESD event evaluation and device characterization. SPICE-like software ADICE is for back-end simulation.Electrostatic Discharges (ESD) is one of the hazard that may affect IC circuit function and cause serious damage to the chip. The importance of ESD protection has been raised since the CMOS technology advanced and the dimension of transistors scales down. On the other hand, the variety of applications of chips is also making corresponding ESD protection difficult to meet different design requirement. Aside from typical requirements such as core circuit operation voltage, maximum accepted leakage current, breakdown conditions for the process and overall device sizes, special applications like radio frequency and power electronic requires ESD to be low parasitic capacitance and can sustain high level energy. In that case, a proper ESD protection design demands not only a robust ESD protection scheme, but co-design with the inner circuit. For that purpose, it is necessary to simulate the results of ESD impact on IC and find out possible weak point of the circuit and improve it. The first step of the simulation is to have corresponding models available. Unfortunately, ESD models, especially there are lack of circuit-level ESD models that provide quick and accurate prediction of ESD event.In this dissertation paper, ESD models, especially ESD failure models for device thermal failure are introduced, with modeling methodology accordingly. First, an introduction for ESD event and typical ESD protection schemes are introduced. Its purpose is to give basic concept of ESD. For ESD failure models, two typical types can be categorized depends on the physical mechanisms that cause the ESD damage. One is the gate oxide breakdown, which is electric field related. The other is the thermal-related failure, which stems from the self-heating effect associated with the large current passing through the ESD protection structure. The first one has become increasingly challenging with the aggressive scaling of the gate dielectric in advanced processes and ESD protection for that need to be carefully designed. The second one, thermal failure widely exists in semiconductor devices as long as there is ESD current flow through the device and accumulate heat at junctions. Considering the universality of thermal failure in ESD device, it is imperative to establish a model to simulate ESD caused thermal failure.Several works related to ESD model can be done. One crucial part for a failure model is to define the failure criterion. As common solution for ESD simulation and failure prediction. The maximum current level or breakdown voltage is used to judge whether a device fails under ESD stresses. Such failure criteria based on measurable voltage or current values are straightforward and can be easy to implemented in simulation tools. However, the shortcoming of these failure criteria is each failure criterion is specifically designed for certain ESD stress condition. For example, the failure voltage level for Human Body Model and Charged Device Model are quite different, and it is hard to judge a device's ESD capability under standard test conditions based on its transmission line pulse test result. So it is necessary to look deeper into the physical mechanism of device failure under ESD and find a more universal failure criterion for various stress conditions.As one of the major failure mechanisms, thermal failure evaluated by temperature is a more universal failure criterion for device failure under ESD stress. Whatever the stress model is, the device will fail if a critical temperature is reached at certain part inside the device and cause structural damage. Then finding out that critical temperature is crucial to define the failure point for device thermal failure. One chapter of this dissertation will focus on discussing this issue and propose a simple method to give close estimation of the real failure temperature for typical ESD devices.Combined these related works, a comprehensive diode model for ESD simulation is proposed. Using existing ESD models, diode I-V characteristic from low current turn-on to high current saturation can be simulated. By using temperature as the failure criterion, the last point of diode operation, or the second breakdown point, can be accurately predicted. Additional investigation of ESD capability of devices for special case like vertical GaN diode is discussed in Chapter IV. Due to the distinct material property of GaN, the vertical GaN diode exhibits unique and interesting quasi-static I-V curves quite different from conventional silicon semiconductor devices. And that I-V curve varies with different pulse width, indicating strong conductivity modulation of diode neutral region that will delay the complete turn-on of the vertical GaN diode.
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Date Issued: 2017
Identifier: CFE0006626, ucf:51291
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006626

Title: Performance optimization of lateral-mode thin-film piezoelectric-on-substrate resonant systems.
Creator: Fatemi, Hedy, Abdolvand, Reza, Sundaram, Kalpathy, Malocha, Donald, Gong, Xun, Cho, Hyoung Jin, University of Central Florida
Abstract / Description: The main focus of this dissertation is to characterize and improve the performance of thin-film piezoelectric-on-substrate (TPoS) lateral-mode resonators and filters. TPoS is a class of piezoelectric MEMS devices which benefits from the high coupling coefficient of the piezoelectric transduction mechanism while taking advantage of superior acoustic properties of a substrate. The use of lateral-mode TPoS designs allows for fabrication of dispersed-frequency filters on a single substrate, thus...
Show moreThe main focus of this dissertation is to characterize and improve the performance of thin-film piezoelectric-on-substrate (TPoS) lateral-mode resonators and filters. TPoS is a class of piezoelectric MEMS devices which benefits from the high coupling coefficient of the piezoelectric transduction mechanism while taking advantage of superior acoustic properties of a substrate. The use of lateral-mode TPoS designs allows for fabrication of dispersed-frequency filters on a single substrate, thus significantly reducing the size and manufacturing cost of devices. TPoS filters also offer a lower temperature coefficient of frequency, and better power handling capability compared to rival technologies all in a very small footprint.Design and fabrication process of the TPoS devices is discussed. Both silicon and diamond substrates are utilized for fabrication of TPoS devices and results are compared. Specifically, the superior acoustic properties of nanocrystalline diamond in scaling the frequency and energy density of the resonators is highlighted in comparison with silicon. The performance of TPoS devices in a variety of applications is reported. These applications include lateral-mode TPoS filters with record low IL values (as low as 2dB) and fractional bandwidth up to 1%, impedance transformers, very low phase noise oscillators, and passive wireless temperature sensors.
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Date Issued: 2015
Identifier: CFE0005945, ucf:50805
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005945

Title: Passive, Wireless SAW OFC Strain Sensor and Software Defined Radio Interrogator.
Creator: Humphries, James, Malocha, Donald, Richie, Samuel, Weeks, Arthur, Sundaram, Kalpathy, Saha, Haripada, University of Central Florida
Abstract / Description: Surface acoustic wave (SAW) devices have exhibited unique capabilities to meet the demands for many applications due to the inherent properties of SAW devices and piezoelectric materials. In particular, SAW devices have been adapted as sensors that can be configured to operate both passively and wirelessly. SAW sensors can be operated in harsh environmental extremes where typical sensor technologies are not able to operate. Because the sensors are passive, a radio transceiver is required to...
Show moreSurface acoustic wave (SAW) devices have exhibited unique capabilities to meet the demands for many applications due to the inherent properties of SAW devices and piezoelectric materials. In particular, SAW devices have been adapted as sensors that can be configured to operate both passively and wirelessly. SAW sensors can be operated in harsh environmental extremes where typical sensor technologies are not able to operate. Because the sensors are passive, a radio transceiver is required to interrogate the sensor and receive the reflected response that has been modulated by the SAW device. This dissertation presents the design of a passive, wireless SAW OFC strain sensor and software defined radio (SDR) interrogator.A SAW strain sensor has been designed and tested using orthogonal frequency coding (OFC) on YZ-LiNbO3. OFC for SAW devices has been previously developed at UCF and provides both frequency and time diversity in the RFID code as well as providing processing gain to improve the sensor SNR. Strain effects in SAW devices are discussed and two sensor embodiments are developed. The first embodiment is a cantilever structure and provides insight on how strain effects the SAW device. The second embodiment bonds the SAW die directly to a test structure to measure the strain on the structure. A commercial wired foil strain gage provides a performance comparison and shows that the wireless SAW sensor performs comparably. A commercial-off-the-shelf SDR platform has been employed as the SAW sensor interrogator. The Universal Software Radio Peripheral (USRP) is available in many embodiments and is capable of operation of to 6GHz and up to 160MHz of bandwidth. In particular, the USRP B200 is utilized as the RF transceiver platform. Custom FPGA modifications are discussed to fully utilize the USRP B200 bandwidth (56MHz) and synchronize the transmit and receive chains. External hardware has also been introduced to the B200 to improve RF performance, all of which are incorporated into a custom enclosure. Post-processing of the SAW sensor response is accomplished in Python using a matched filter correlator routine to extract sensor information. The system is demonstrated by interrogating wireless OFC SAW temperature and strain sensors at 915MHz.
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Date Issued: 2016
Identifier: CFE0006329, ucf:51560
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006329

Title: Deposition and characterization studies of boron carbon nitride (BCN) thin films prepared by dual target sputtering.
Creator: Prakash, Adithya, Sundaram, Kalpathy, Kapoor, Vikram, Yuan, Jiann-Shiun, Jin, Yier, Chow, Louis, University of Central Florida
Abstract / Description: As complementary metal-oxide semiconductor (CMOS) devices shrink to smaller size, the problems related to circuit performance such as critical path signal delay are becoming a pressing issue. These delays are a result of resistance and capacitance product (RC time constant) of the interconnect circuit. A novel material with reduced dielectric constants may compromise both the thermal and mechanical properties that can lead to die cracking during package and other reliability issues. Boron...
Show moreAs complementary metal-oxide semiconductor (CMOS) devices shrink to smaller size, the problems related to circuit performance such as critical path signal delay are becoming a pressing issue. These delays are a result of resistance and capacitance product (RC time constant) of the interconnect circuit. A novel material with reduced dielectric constants may compromise both the thermal and mechanical properties that can lead to die cracking during package and other reliability issues. Boron carbon nitride (BCN) compounds have been expected to combine the excellent properties of boron carbide (B4C), boron nitride (BN) and carbon nitride (C3N4), with their properties adjustable, depending on composition and structure. BCN thin film is a good candidate for being hard, dense, pore-free, low-k dielectric with values in the range of 1.9 to 2.1. Excellent mechanical properties such as adhesion, high hardness and good wear resistance have been reported in the case of sputtered BCN thin films. Problems posed by high hardness materials such as diamonds in high cutting applications and the comparatively lower hardness of c-BN gave rise to the idea of a mixed phase that can overcome these problems with a minimum compromise in its properties. A hybrid between semi-metallic graphite and insulating h-BN may show adjusted semiconductor properties. BCN exhibits the potential to control optical bandgap (band gap engineering) by atomic composition, hence making it a good candidate for electronic and photonic devices. Due to tremendous bandgap engineering capability and refractive index variability in BCN thin film, it is feasible to develop filters and mirrors for use in ultra violet (UV) wavelength region. It is of prime importance to understand process integration challenges like deposition rates, curing, and etching, cleaning and polishing during characterization of low-k films. The sputtering technique provides unique advantages over other techniques such as freedom to choose the substrate material and a uniform deposition over relatively large area. BCN films are prepared by dual target reactive magnetron sputtering from a B4C and BN targets using DC and RF powers respectively. In this work, an investigation of mechanical, optical, chemical, surface and device characterizations is undertaken. These holistic and thorough studies, will provide the insight into the capability of BCN being a hard, chemically inert, low-k, wideband gap material, as a potential leader in semiconductor and optics industry.
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Date Issued: 2016
Identifier: CFE0006378, ucf:51496
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006378

Title: Precision Metrology of Laser Plasmas in the XUV Band.
Creator: Szilagyi, John, Richardson, Martin, Sundaram, Kalpathy, Abdolvand, Reza, Baudelet, Matthieu, Shivamoggi, Bhimsen, University of Central Florida
Abstract / Description: The XUV band, a region of light spanning the wavelength range of 5 - 200 nm, is located between the Ultraviolet and X-ray regions of the electromagnetic spectrum. It is further divided into a 100 - 200 nm region called the Vacuum Ultraviolet (VUV), and a 5 (-) 100 nm region called the Extreme Ultraviolet (EUV). Applications of this light have been slow to develop due to the lack of suitable sources, efficient optics, and sensitive detectors. Recently, many industries such as the semiconductor...
Show moreThe XUV band, a region of light spanning the wavelength range of 5 - 200 nm, is located between the Ultraviolet and X-ray regions of the electromagnetic spectrum. It is further divided into a 100 - 200 nm region called the Vacuum Ultraviolet (VUV), and a 5 (-) 100 nm region called the Extreme Ultraviolet (EUV). Applications of this light have been slow to develop due to the lack of suitable sources, efficient optics, and sensitive detectors. Recently, many industries such as the semiconductor manufacturing industry, medical surgery, micromachining, microscopy, and spectroscopy have begun to benefit from the short wavelengths and the high photon energies of this light. At present, the semiconductor chip industry is the primary reason for the investment in, and development of, XUV sources, optics, and detectors. The demand for high power EUV light sources at 13.5 nm wavelength is driven by the development of the next generation of semiconductor lithography tools. The development of these tools enables the continued reduction in size, and the increase in transistor density of semiconductor devices on a single chip. Further development and investigation of laser produced plasma EUV light sources is necessary to increase the average optical power and reliability. This will lead to an increase in the speed of EUV lithographic processes, which are necessary for future generations of advanced chip design, and high volume semiconductor manufacturing. Micromachining, lithography, and microscopy benefit from improvements in resolution due to the shorter wavelengths of light in the VUV band. In order to provide adequate illumination for these applications, sources are required which are brighter and have higher average power. Laser produced plasma (LPP) VUV light sources are used extensively for lithography and defect detection in semiconductor manufacturing. Reductions in the wavelength and increases in the average power will increase the rate and yield of chip manufacture, as well as reduce the costs of semiconductor manufacture.The work presented in this thesis, describes the development of two laser plasma source facilities in the Laser Plasma Laboratory at UCF, which were designed to investigate EUV and VUV laser plasma sources. The HP-EUV-Facility was developed to optimize and demonstrate a high power 13.5 nm EUV LPP source. This facility provides high resolution spectroscopy across 10.5 - 20 nm, and absolute energy measurement of 13.5 nm +/- 2% in 2? sr. The VUV-MS-Facility was developed to investigate VUV emission characteristics of laser plasmas of various target geometries and chemistries. This facility provides absolute calibrated emission spectra for the 124 - 250 nm wavelength range, in addition to, at wavelength plasma imaging. Calibrated emission spectra, in-band power, and conversion efficiency are presented in this work for gas targets of Argon, Krypton, and Xenon and solid targets of Silicon, Copper, Molybdenum, Indium, Tantalum, Tin, and Zinc, across the laser intensity range of 8.0x10^6 (-) 3.2x10^12 W/cm2.
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Date Issued: 2017
Identifier: CFE0006805, ucf:51793
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006805

Title: The Effect of Morphology on Reflectance in Silicon Nanowires Grown by Electroless Etching.
Creator: Velez, Victor, Sundaram, Kalpathy, Kapoor, Vikram, Yuan, Jiann-Shiun, Abdolvand, Reza, Kar, Aravinda, University of Central Florida
Abstract / Description: The strong light trapping properties of Silicon Nanowires have attracted much interest in the past few years for the conversion of sun energy into conventional electricity. Studies have been completed for many researchers to reduce the cost of fabrication and reflectance of solar light in these nanostructures to make a cheaper and more efficient solar cell technology by using less equipment for fabrication and employing different materials and solution concentrations. Silver, a conducting and...
Show moreThe strong light trapping properties of Silicon Nanowires have attracted much interest in the past few years for the conversion of sun energy into conventional electricity. Studies have been completed for many researchers to reduce the cost of fabrication and reflectance of solar light in these nanostructures to make a cheaper and more efficient solar cell technology by using less equipment for fabrication and employing different materials and solution concentrations. Silver, a conducting and stable metal is used these days as a precursor to react with silicon and then form the nanowires. Its adequate selection of solution concentration for a size of silicon substrate and the treatment for post-cleaning of silver dendrites make it a viable method among the others. It is an aim of this research to obtain significant low reflectance across the visible solar light range. Detailed concentration, fabrication and reflectance studies is carried out on silicon wafer in order to expand knowledge and understanding.In this study, electroless etching technique has been used as the growth mechanism of SiNWs at room temperature. Optimum ratios of solution concentration and duration for different sizes of exposed area to grow tall silicon nanowires derived from experimentation are presented. Surface imaging of the structures and dimension of length and diameter have been determined by Scanner Electron Microscopy (SEM) and the reflectance in the optical range in silicon nanowires has been make using UV-Visible Spectrophotometer.
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Date Issued: 2017
Identifier: CFE0006815, ucf:51807
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006815

Title: Advanced Metrology and Diagnostic Loss Analytics for Crystalline Silicon Photovoltaics.
Creator: Schneller, Eric, Schoenfeld, Winston, Thomas, Jayan, Fenton, James, Coffey, Kevin, Sundaram, Kalpathy, University of Central Florida
Abstract / Description: Characterization plays a key role in developing a comprehensive understanding of the structure and performance of photovoltaic devices. High quality characterization methods enable researchers to assess material choices and processing steps, ultimately giving way to improved device performance and reduced manufacturing costs. In this work, several aspects of advanced metrology for crystalline silicon photovoltaic are investigated including in-line applications for manufacturing, off-line...
Show moreCharacterization plays a key role in developing a comprehensive understanding of the structure and performance of photovoltaic devices. High quality characterization methods enable researchers to assess material choices and processing steps, ultimately giving way to improved device performance and reduced manufacturing costs. In this work, several aspects of advanced metrology for crystalline silicon photovoltaic are investigated including in-line applications for manufacturing, off-line applications for research and development, and module/system level applications to evaluate long-term reliability. A frame work was developed to assess the cost and potential value of metrology within a manufacturing line. This framework has been published to an on-line calculator in an effort to provide the solar industry with an intuitive and transparent method of evaluating the economics of in-line metrology. One important use of metrology is in evaluating spatial non-uniformities, as localized defects in large area solar cells often reduce overall device performance. Techniques that probe spatial uniformity were explored and analysis algorithms were developed that provide insights regarding process non-uniformity and its impact on device performance. Finally, a comprehensive suite of module level characterization was developed to accurately evaluate performance and identify degradation mechanisms in field deployed photovoltaic modules. For each of these applications, case-studies were used to demonstrate the value of these techniques and to highlight potential use cases.
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Date Issued: 2016
Identifier: CFE0006499, ucf:51386
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006499

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RF (2)	+ -
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