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- Title
- CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY.
- Creator
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Kutty, Karan, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
-
This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were...
Show moreThis study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
Show less - Date Issued
- 2010
- Identifier
- CFE0003360, ucf:48477
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003360
- Title
- CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
- Creator
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Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
Show less - Date Issued
- 2011
- Identifier
- CFE0003595, ucf:48861
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003595
- Title
- INVESTIGATION AND TRADE STUDY ON HOT CARRIER RELIABILITY OF THE PHEMT FOR DC AND RF PERFORMANCE.
- Creator
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Steighner, Jason, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe...
Show moreA unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstrate the performance degradation that occurs after a period of operation in an accelerated stress regime-one hour of high drain voltage, low drain current stress. This stress regime and normal operation regime are then modeled through Sentaurus. Output characteristics are shown along with stress mechanisms within the device. Lastly, a means of simulating a PHEMT post-stress is introduced. The approach taken accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance are then investigated.
Show less - Date Issued
- 2011
- Identifier
- CFE0003994, ucf:48659
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003994
- Title
- Artificial Neuron using MoS2/Graphene Threshold Switching Memristor.
- Creator
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Kalita, Hirokjyoti, Roy, Tania, Sundaram, Kalpathy, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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With the ever-increasing demand for low power electronics, neuromorphic computing has garnered huge interest in recent times. Implementing neuromorphic computing in hardware will be a severe boost for applications involving complex processes such as pattern recognition. Artificial neurons form a critical part in neuromorphic circuits, and have been realized with complex complementary metal(-)oxide(-)semiconductor (CMOS) circuitry in the past. Recently, insulator-to-metal-transition (IMT)...
Show moreWith the ever-increasing demand for low power electronics, neuromorphic computing has garnered huge interest in recent times. Implementing neuromorphic computing in hardware will be a severe boost for applications involving complex processes such as pattern recognition. Artificial neurons form a critical part in neuromorphic circuits, and have been realized with complex complementary metal(-)oxide(-)semiconductor (CMOS) circuitry in the past. Recently, insulator-to-metal-transition (IMT) materials have been used to realize artificial neurons. Although memristors have been implemented to realize synaptic behavior, not much work has been reported regarding the neuronal response achieved with these devices. In this work, we study the IMT in 1T-TaS2 and the volatile threshold switching behavior in vertical-MoS2 (v-MoS2) and graphene van der Waals heterojunction system. The v-MoS2/graphene threshold switching memristor (TSM) is used to produce the integrate-and-fire response of a neuron. We use large area chemical vapor deposited (CVD) graphene and MoS2, enabling large scale realization of these devices. These devices can emulate the most vital properties of a neuron, including the all or nothing spiking, the threshold driven spiking of the action potential, the post-firing refractory period of a neuron and strength modulated frequency response. These results show that the developed artificial neuron can play a crucial role in neuromorphic computing.
Show less - Date Issued
- 2018
- Identifier
- CFE0007203, ucf:52291
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007203
- Title
- "Design and Simulation of CMOS RF Active Mixers".
- Creator
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Gibson, Allen, Yuan, Jiann-Shiun, Wei, Lei, Sundaram, Kalpathy, University of Central Florida
- Abstract / Description
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This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage...
Show moreThis paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 (&)#181;m CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.
Show less - Date Issued
- 2011
- Identifier
- CFE0004112, ucf:49086
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004112
- Title
- Lateral Power MOSFETs Hardened Against Single Event Radiation Effects.
- Creator
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Shea, Patrick, Shen, Zheng, Yuan, Jiann-Shiun, Malocha, Donald, University of Central Florida
- Abstract / Description
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The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard...
Show moreThe underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metrics.
Show less - Date Issued
- 2011
- Identifier
- CFE0004165, ucf:49044
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004165
- Title
- Simulation Study of a GPRAM System: Error Control Coding and Connectionism.
- Creator
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Schultz, Steven, Wei, Lei, Lin, Mingjie, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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A new computing platform, the General Purpose Reprsentation and Association Machine is studied and simulated. GPRAM machines use vague measurements to do a quick and rough assessment on a task; then use approximated message-passing algorithms to improve assessment; and finally selects ways closer to a solution, eventually solving it. We illustrate concepts and structures using simple examples.
- Date Issued
- 2012
- Identifier
- CFE0004437, ucf:49361
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004437
- Title
- Design and Characterization of High Temperature Packaging for Wide-Bandgap Semiconductor Devices.
- Creator
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Grummel, Brian, Shen, Zheng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor...
Show moreAdvances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au(-)In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au(-)In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermo-mechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.
Show less - Date Issued
- 2012
- Identifier
- CFE0004499, ucf:49276
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004499
- Title
- Load Estimation for Electric Power Distribution Networks.
- Creator
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Eyisi, Chiebuka, Lotfifard, Saeed, Yuan, Jiann-Shiun, Wu, Xinzhang, University of Central Florida
- Abstract / Description
-
In electric power distribution systems, the major determinant in electricity supply strategy is the quantity of demand. Customers need to be accurately represented using updated nodal load information as a requirement for efficient control and operation of the distribution network. In Distribution Load Estimation (DLE), two major categories of data are utilized: historical data and direct real-time measured data. In this thesis, a comprehensive survey on the state-of-the-art methods for...
Show moreIn electric power distribution systems, the major determinant in electricity supply strategy is the quantity of demand. Customers need to be accurately represented using updated nodal load information as a requirement for efficient control and operation of the distribution network. In Distribution Load Estimation (DLE), two major categories of data are utilized: historical data and direct real-time measured data. In this thesis, a comprehensive survey on the state-of-the-art methods for estimating loads in distribution networks is presented. Then, a novel method for representing historical data in the form of Representative Load Curves (RLCs) for use in real-time DLE is also described. Adaptive Neuro-Fuzzy Inference Systems (ANFIS) is used in this regard to determine RLCs. An RLC is a curve that represents the behavior of the load during a specified time span; typically daily, weekly or monthly based on historical data. Although RLCs provide insight about the variation of load, it is not accurate enough for estimating real-time load. This therefore, should be used along with real-time measurements to estimate the load more accurately. It is notable that more accurate RLCs lead to better real-time load estimation in distribution networks.This thesis addresses the need to obtain accurate RLCs to assist in the decision-making process pertaining to Radial Distribution Networks (RDNs).This thesis proposes a method based on Adaptive Neuro-Fuzzy Inference Systems (ANFIS) architecture to estimate the RLCs for Distribution Networks. The performance of the method is demonstrated and simulated, on a test 11kV Radial Distribution Network using the MATLAB software. The Mean Absolute Percent Error (MAPE) criterion is used to justify the accuracy of the RLCs.
Show less - Date Issued
- 2013
- Identifier
- CFE0004995, ucf:49555
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004995
- Title
- Work Function Extraction of Indium Tin Oxide Used As Transparent Gate Electrode For MOSFET.
- Creator
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Nehate, Shraddha, Sundaram, Kalpathy, Kapoor, Vikram, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
-
Recent commercialization has peaked interest in transparent conducting oxides being implemented in display technology. Indium Tin Oxide (ITO) is a popular transparent conducting oxide which has been utilized as high work function electrode in liquid crystal displays, solar cells, gas sensors and heat reflecting films. Indium Tin Oxide films exhibit excellent transmission characteristics in the visible and infrared spectrum while maintaining high electrical conductivity. High work function...
Show moreRecent commercialization has peaked interest in transparent conducting oxides being implemented in display technology. Indium Tin Oxide (ITO) is a popular transparent conducting oxide which has been utilized as high work function electrode in liquid crystal displays, solar cells, gas sensors and heat reflecting films. Indium Tin Oxide films exhibit excellent transmission characteristics in the visible and infrared spectrum while maintaining high electrical conductivity. High work function electrodes are used to inject holes into organic materials. In majority applications the ITO work function has an impact on the device performance as it affects the energy barrier height at the hetero-junction interface. Hence, the work function of ITO is of critical importance.In this thesis, the work function of ITO is extracted successfully from a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device for the first time. Two MOSFET devices are fabricated using a four level mask under exact same conditions. Aluminum metal is used as a drain and source contact for both MOSFETs. One of the MOSFET has aluminum gate contact and transparent conducting ITO is used as gate contact for the second MOSFET. From the threshold voltage equation of both the fabricated MOSFETs, work function of ITO is extracted. Further optical transmission studies of ITO performed in the visible spectra are also reported in this study.
Show less - Date Issued
- 2016
- Identifier
- CFE0006364, ucf:51534
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006364
- Title
- Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation.
- Creator
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Mendoza Macias, Raul, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Fan, Deliang, University of Central Florida
- Abstract / Description
-
Vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In...
Show moreVertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In addition, electrical parameters such as threshold voltage and charge balance are also examined. Increasing the superjunction doping in the drift region of VDMOS reduces the on-resistance by 26%, while maintaining the same breakdown voltage and threshold voltage compared to that of the conventional VDMOS power transistor with similar device design without using a superjunction.
Show less - Date Issued
- 2016
- Identifier
- CFE0006354, ucf:51525
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006354
- Title
- Three-Dimensional Simulation Study of Low Voltage ((<)100V) Superjunction Lateral DMOS power transistors.
- Creator
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Garcia, Jhonatan, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Fan, Deliang, University of Central Florida
- Abstract / Description
-
A new revolutionary concept was presented two decades ago, known as (")semiconductor Superjunction (SJ) theory(") to enhance the trade-off relationship between speci?c on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was ?rst applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures,...
Show moreA new revolutionary concept was presented two decades ago, known as (")semiconductor Superjunction (SJ) theory(") to enhance the trade-off relationship between speci?c on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was ?rst applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures, principles and design techniques for discrete power MOSFETs. It also presents a simulation study of the application of these SJ concepts in the design of a Low Voltage SJ LDMOS transistor, using TCAD software. To make the device commercially feasible, this device design targets aggressive goals such as an off-state Breakdown Voltage of 60V with Rspof 20 miliohms per milimiter square. This study includes the analysis of the ?ow process for the fabrication of this transistor, using semiconductor technologies, and the simulation results, including Breakdown Voltage, on-state resistance, electric ?eld distribution among others simulation analysis.
Show less - Date Issued
- 2016
- Identifier
- CFE0006306, ucf:51600
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006306
- Title
- LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation.
- Creator
-
Salih, Aiman, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Kapoor, Vikram, University of Central Florida
- Abstract / Description
-
The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ...
Show moreThe benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance (&)#215; gate charge) of 5.93 m?-nC.
Show less - Date Issued
- 2017
- Identifier
- CFE0006955, ucf:51673
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006955
- Title
- Investigation on electrical properties of RF sputtered deposited BCN thin films.
- Creator
-
Prakash, Adithya, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Lin, Mingjie, University of Central Florida
- Abstract / Description
-
The ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated...
Show moreThe ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated circuit (ULSI) devices. In order to reduce the time delay, it is necessary to introduce a wiring metal with low resistivity and a high quality insulating film with a low dielectric constant which leads to a reduction of the wiring capacitance.Boron carbon nitride (BCN) films are prepared by reactive magnetron sputtering from a B(&)#172;4C target and deposited to make metal-insulator-metal (MIM) sandwich structures using aluminum as the top and bottom electrodes. BCN films are deposited at various N2/Ar gas flow ratios, substrate temperatures and process pressures. The electrical characterization of the MIM devices includes capacitance vs. voltage (C-V), current vs voltage, and breakdown voltage characteristics. The above characterizations are performed as a function of deposition parameters.
Show less - Date Issued
- 2013
- Identifier
- CFE0004912, ucf:49625
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004912
- Title
- Semiconductor Design and Manufacturing Interplay to Achieve Higher Yields at Reduced Costs using SMART Techniques.
- Creator
-
Oberai, Ankush Bharati, Yuan, Jiann-Shiun, Abdolvand, Reza, Georgiopoulos, Michael, Sundaram, Kalpathy, Reilly, Charles, University of Central Florida
- Abstract / Description
-
Since the outset of IC Semiconductor market there has been a gap between its design and manufacturing communities. This gap continued to grow as the device geometries started to shrink and the manufacturing processes and tools got more complex. This gap lowered the manufacturing yield, leading to higher cost of ICs and delay in their time to market. It also impacted performance of the ICs, impacting the overall functionality of the systems they were integrated in. However, in the recent years...
Show moreSince the outset of IC Semiconductor market there has been a gap between its design and manufacturing communities. This gap continued to grow as the device geometries started to shrink and the manufacturing processes and tools got more complex. This gap lowered the manufacturing yield, leading to higher cost of ICs and delay in their time to market. It also impacted performance of the ICs, impacting the overall functionality of the systems they were integrated in. However, in the recent years there have been major efforts to bridge the gap between design and manufacturing using software solutions by providing closer collaborations techniques between design and manufacturing communities. The root cause of this gap is inherited by the difference in the knowledge and skills required by the two communities. The IC design community is more microelectronics, electrical engineering and software driven whereas the IC manufacturing community is more driven by material science, mechanical engineering, physics and robotics. The cross training between the two is almost nonexistence and not even mandated. This gap is deemed to widen, with demand for more complex designs and miniaturization of electronic appliance-products. Growing need for MEMS, 3-D NANDS and IOTs are other drivers that could widen the gap between design and manufacturing. To bridge this gap, it is critical to have close loop solutions between design and manufacturing This could be achieved by SMART automation on both sides by using Artificial Intelligence, Machine Learning and Big Data algorithms. Lack of automation and predictive capabilities have even made the situation worse on the yield and total turnaround times. With the growing fabless and foundry business model, bridging the gap has become even more critical. Smart Manufacturing philosophy must be adapted to make this bridge possible. We need to understand the Fab-fabless collaboration requirements and the mechanism to bring design to the manufacturing floor for yield improvement. Additionally, design community must be educated with manufacturing process and tool knowledge, so they can design for improved manufacturability. This study will require understanding of elements impacting manufacturing on both ends of the design and manufacturing process. Additionally, we need to understand the process rules that need to be followed closely in the design phase. Best suited SMART automation techniques to bridge the gap need to be studied and analyzed for their effectiveness.
Show less - Date Issued
- 2018
- Identifier
- CFE0007351, ucf:52096
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007351
- Title
- Design and Implementation of PV-Firming and Optimization Algorithms For Three-Port Microinverters.
- Creator
-
Alharbi, Mahmood, Batarseh, Issa, Haralambous, Michael, Mikhael, Wasfy, Yuan, Jiann-Shiun, Kutkut, Nasser, University of Central Florida
- Abstract / Description
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With the demand increase for electricity, the ever-increasing awareness of environmental issues, coupled with rolling blackouts, the role of renewable energy generation is increasing along with the thirst for electricity and awareness of environmental issues. This dissertation proposes the design and implementation of PV-firming and optimization algorithms for three-port microinverters.Novel strategies are proposed in Chapters 3 and 4 for harvesting stable solar power in spite of intermittent...
Show moreWith the demand increase for electricity, the ever-increasing awareness of environmental issues, coupled with rolling blackouts, the role of renewable energy generation is increasing along with the thirst for electricity and awareness of environmental issues. This dissertation proposes the design and implementation of PV-firming and optimization algorithms for three-port microinverters.Novel strategies are proposed in Chapters 3 and 4 for harvesting stable solar power in spite of intermittent solar irradiance. PV firming is implemented using a panel-level three-port grid-tied PV microinverter system instead of the traditional high-power energy storage and management system at the utility scale. The microinverter system consists of a flyback converter and an H-bridge inverter/rectifier, with a battery connected to the DC-link. The key to these strategies lies in using static and dynamic algorithms to generate a smooth PV reference power. The outcomes are applied to various control methods to charge/discharge the battery so that a stable power generation profile is obtained. In addition, frequency-based optimization for the inverter stage is presented.One of the design parameters of grid-tied single-phase H-bridge sinusoidal pulse-width modulation (SPWM) microinverters is switching frequency. The selection of the switching frequency is a tradeoff between improving the power quality by reducing the total harmonic distortion (THD), and improving the efficiency by reducing the switching loss. In Chapter 5, two algorithms are proposed for optimizing both the power quality and the efficiency of the microinverter. They do this by using a frequency tracking technique that requires no hardware modification. The first algorithm tracks the optimal switching frequency for maximum efficiency at a given THD value. The second maximizes the power quality of the H-bridge micro-inverter by tracking the switching frequency that corresponds to the minimum THD.Real-time PV intermittency and usable capacity data were evaluated and then further analyzed in MATLAB/SIMULINK to validate the PV firming control. The proposed PV firming and optimization algorithms were experimentally verified, and the results evaluated. Finally, Chapter 6 provides a summary of key conclusions and future work to optimize the presented topology and algorithms.
Show less - Date Issued
- 2018
- Identifier
- CFE0007305, ucf:52166
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007305
- Title
- HIGH QUALITY GATE DIELECTRIC/MoS2 INTERFACES PROBED BY THE CONDUCTANCE METHOD.
- Creator
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Krishnaprasad Sharada, Adithi Pandrahal, Roy, Tania, Abdolvand, Reza, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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Two-dimensional materials provide a versatile platform for various electronic and optoelectronic devices, due to their uniform thickness and pristine surfaces. We probe the superior quality of 2D/2D and 2D/3D interfaces by fabricating molybdenum disulfide (MoS2)-based field effect transistors having hexagonal boron nitride (h-BN) and Al2O3 as the top gate dielectrics. An extremely low trap density of ~7x10^10 states/cm2-eV is extracted at the 2D/2D interfaces with h-BN as the top gate...
Show moreTwo-dimensional materials provide a versatile platform for various electronic and optoelectronic devices, due to their uniform thickness and pristine surfaces. We probe the superior quality of 2D/2D and 2D/3D interfaces by fabricating molybdenum disulfide (MoS2)-based field effect transistors having hexagonal boron nitride (h-BN) and Al2O3 as the top gate dielectrics. An extremely low trap density of ~7x10^10 states/cm2-eV is extracted at the 2D/2D interfaces with h-BN as the top gate dielectric on the MoS2 channel. 2D/3D interfaces with Al2O3 as the top gate dielectric and SiOx as the nucleation layer exhibit trap densities between 7x10^10 and 10^11 states/cm2-eV, which is lower than previously reported 2D-channel/high-k-dielectric interface trap densities. The comparable values of trap time constants for both interfaces imply that similar types of defects contribute to the interface traps. This work establishes the case for van der Waals systems where the superior quality of 2D/2D and 2D/high-k dielectric interfaces can produce high performance electronic and optoelectronic devices.
Show less - Date Issued
- 2018
- Identifier
- CFE0007214, ucf:52209
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007214
- Title
- GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs.
- Creator
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Binder, Andrew, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Roy, Tania, Kapoor, Vikram, Chow, Lee, University of Central Florida
- Abstract / Description
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GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is...
Show moreGaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ((<) 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition.
Show less - Date Issued
- 2019
- Identifier
- CFE0007885, ucf:52786
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007885
- Title
- The Performance and Power Impact of Using Multiple DRAM Address Mapping Schemes in Multicore Processors.
- Creator
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Jadaa, Rami, Heinrich, Mark, DeMara, Ronald, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic...
Show moreLowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications' performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing un-accessed devices to be put into power-down mode, hence saving power to meet a certain power budget.
Show less - Date Issued
- 2011
- Identifier
- CFE0004121, ucf:49118
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004121
- Title
- Design, Characterization and Analysis of Electrostatic Discharge (ESD) Protection Solutions in Emerging and Modern Technologies.
- Creator
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Liu, Wen, Liou, Juin, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Chen, Quanfang, University of Central Florida
- Abstract / Description
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Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and...
Show moreElectrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal(-)oxide(-)semiconductor (CMOS) technologies.The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diode-triggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end.
Show less - Date Issued
- 2012
- Identifier
- CFE0004571, ucf:49199
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004571
