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Gate and throughput optimizations for null convention self-timed digital circuits
Title
Gate and throughput optimizations for null convention self-timed digital circuits.
Creator
Smith, Scott Christopher, DeMara, Ronald, Engineering and Computer Science
Abstract / Description
University of Central Florida College of Engineering Thesis; Convention Logic (NCL) provides an asynchronous design methodology employing dual-rail signals, quad-rail signals, or other Mutually Exclusive Assertion Groups (MEAGs) to incorporate data and control information into one mixed path. In NCL, the control is inherently present with each datum, so there is no need for worse case delay analysis and control path delay matching. This dissertation focuses on optimization methods for NCL...
Show moreUniversity of Central Florida College of Engineering Thesis; Convention Logic (NCL) provides an asynchronous design methodology employing dual-rail signals, quad-rail signals, or other Mutually Exclusive Assertion Groups (MEAGs) to incorporate data and control information into one mixed path. In NCL, the control is inherently present with each datum, so there is no need for worse case delay analysis and control path delay matching. This dissertation focuses on optimization methods for NCL circuits, specifically addressing three related architectural areas of NCL design. First, a design method for optimizing NCL circuits is developed. The method utilizes conventional Boolean minimization followed by table-driven gate substitutions. It IS applied to design time and space optimal fundamental logic functions, a time and space optimal full adder, and time, transistor count, and power optimal up-counter circuits. The method is applicable when composing logic functions where each gate is a state-holding element; and can produce delay-insensitive circuits requiring less area and fewer gate delays than alternative gate-level approaches requiring full minterm generation. Second, a pipelining method for producing throughput optimal NCL systems is developed. A relationship between the number of gate delays per stage and the worse case throughput for a pipeline as a whole is derived. The method then uses this relationship to minimize a pipeline's worse-case throughput by partitioning the NCL combinational circuitry through the addition of asynchronous registers. The method is applied to design a maximum throughput unsigned multiplier, which yields a speedup of 2.25 over the non-pipelined version, while maintaining delay-insensitivity. Third, a technique to mitigate the impact of the NULL cycle is developed. The technique Wher increases the maximum attainable throughput of a NCL system by reducing inherent overheads associated with an integrated data and control path. This technique is applied to a non-pipelined Cbit by 4-bit unsigned multiplier to yield a speedup of 1.61 over the standalone version. Finally, these techniques are applied to design a 72+32x32 multiply and &cumulate (MAC) unit, which outperforms other delay-insensitive/self-timed MACs in the literature. It also performs conditional rounding, scaling, and saturation of the output, whereas the others do not; thus further distinguishing it from the previous work. The methods developed facilitate speed, transistor count, and power tradeoffs using approaches that are readily automatable.
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Date Issued
2001
Identifier
CFR0001377, ucf:52924
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFR0001377
Energy aware design and analysis for synchronous and asynchronous circuits
Title
Energy aware design and analysis for synchronous and asynchronous circuits.
Creator
Di, Jia, Yuan, Jiann S., Engineering and Computer Science
Abstract / Description
University of Central Florida College of Engineering Thesis; Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale...
Show moreUniversity of Central Florida College of Engineering Thesis; Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale with changing conditions and quality requirements. Scalability is an important figure-of-merit since it allows the end user to implement operational policy just like the user of mobile multimedia equipment needs to select between better quality and longer battery operation time. This dissertation discusses power /energy optimization and performs analysis on both synchronous and asynchronous logic.
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Date Issued
2004
Identifier
CFR0001720, ucf:52913
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFR0001720