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OPTIMIZING DYNAMIC LOGIC REALIZATIONS FOR PARTIAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS
Title
OPTIMIZING DYNAMIC LOGIC REALIZATIONS FOR PARTIAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS.
Creator
Parris, Matthew, DeMara, Ronald, University of Central Florida
Abstract / Description
Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device....
Show moreMany digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.
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Date Issued
2008
Identifier
CFE0002323, ucf:47793
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002323
Overexpression of human Cu/Zn Superoxide Dismutase in Mice: A Model to Study the Effect of Increased Superoxide Scavenging on the Autonomic Control of the Heart.
Title
Overexpression of human Cu/Zn Superoxide Dismutase in Mice: A Model to Study the Effect of Increased Superoxide Scavenging on the Autonomic Control of the Heart.
Creator
Hatcher, Jeffrey, Cheng, Zixi, Bossy-Wetzel, Ella, Fernandez-Valle, Cristina, Belfield, Kevin, University of Central Florida
Abstract / Description
Dysregulation of the autonomic cardiovascular control is a complication of diseases including diabetes, hypertension, sleep apnea, and aging. A common factor in these conditions is an increase in reactive oxygen species (ROS) in neural, cardiac, and endothelial tissues. Cu/Zn superoxide dismutase (SOD1) is an intracellular anti-oxidant enzyme that catalyzes dismutation of the superoxide anion (O2.-) to hydrogen peroxide (H2O2). Expression and function of this enzyme are diminished in...
Show moreDysregulation of the autonomic cardiovascular control is a complication of diseases including diabetes, hypertension, sleep apnea, and aging. A common factor in these conditions is an increase in reactive oxygen species (ROS) in neural, cardiac, and endothelial tissues. Cu/Zn superoxide dismutase (SOD1) is an intracellular anti-oxidant enzyme that catalyzes dismutation of the superoxide anion (O2.-) to hydrogen peroxide (H2O2). Expression and function of this enzyme are diminished in pathologies that impair cardiovascular autonomic control. This study employed mice overexpressing a transgene for human SOD1 (hSOD1) to determine if its overexpression would alter autonomic regulation of BP, HR, and BRS in healthy animals, and if this animal line (C57B6SJL-Tg (SOD1)2 Gur/J) could be used in future studies to determine if hSOD1 overexpression can preserve cardiac autonomic function in disease models. To accomplish this aim, using anesthetized SOD1 and C57 (control) mice, we recorded HR, and aortic depressor nerve (ADN) activity changes in response to pharmacologically-induced BP changes in order to measure baroreflex and baroreceptor sensitivity, respectively. In order to identify any alterations in central, efferent, and cardiac components of the baroreflex arc, we electrically stimulated the left ADN and left cervical vagus and compared the reductions in BP and HR between the C57 and SOD1 mice. Time- and frequency-domain analysis of heart rate variability (HRV) was performed using pulse pressure recordings prior to pharmacologic or surgical procedures. We found that hSOD1 overexpression in the SOD1 mouse line, in comparison to C57 controls did not significantly affect resting HR (C57: 558 (&)#177; 8 vs. SOD1:553 (&)#177; 13 beats-per-minute) or blood pressure (C57: 88.8 (&)#177; 2.9 vs.SOD1: 85.8 (&)#177; 2.1 mmHg). hSOD1 overexpression did not affect the decrease in average mean arterial pressure (MAP) following injection of sodium nitroprusside (SNP) (C57: 38.7 (&)#177; 1.4 vs. SOD1: 39.5 (&)#177; 1.3 mmHg) or increase in average MAP (C57: 135.8 (&)#177; 3.1 vs. SOD1: 136.6 (&)#177; 3.5 mmHg) following injection of phenylephrine (PE). BRS, as measured by the averaged regression lines for ?HR/?MAP for the SNP-induced tachycardic baroreflex (C57: 0.57 (&)#177; 0.06 bpm/mmHg, SOD1: 0.61 (&)#177; 0.08 bpm/mmHg)) and the PE-induced bradycardic baroreflex (C57: -2.9 (&)#177; 0.57 bmp/mmHg, SOD1: -4.3 (&)#177; 0.84 bpm/mmHg) are not significantly different between C57 and SOD1. Baroreceptor activation showed a significant increase in gain (C57: 5.4 (&)#177; 0.3 vs. SOD1: 7.4 (&)#177; 0.5 %/mmHg, P (<) 0.01) in the SOD1 transgenic mice. Heart rate depression in response to electrical stimulation of the left ADN and cervical vagus was comparable between C57 and SOD1, though MAP reduction in response to ADN stimulation is slightly, but significantly increased at 50 Hz in SOD1 animals. Time- domain analysis of HRV did not reveal any significant difference in beat-to-beat variability between SOD1 and C57 (SDNN: C57: 2.78 (&)#177; 0.20, SOD1: 2.89 (&)#177; 0.27), although frequency-domain analysis uncovered a significant reduction in the low-frequency power component of the HRV power spectral distribution (C57: 1.19 (&)#177; 0.11, SOD1: 0.35 (&)#177; 0.06, P (<) 0.001). This study shows that although hSOD1 overexpression does not affect overall baroreflex function, it does potentiate baroreceptor sensitivity and brain stem control of arterial pressure, and reduces low-frequency beat-to-beat variations in HR, without affecting total HRV.
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Date Issued
2015
Identifier
CFE0005803, ucf:50025
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0005803
Design Disjunction for Resilient Reconfigurable Hardware
Title
Design Disjunction for Resilient Reconfigurable Hardware.
Creator
Alzahrani, Ahmad, DeMara, Ronald, Yuan, Jiann-Shiun, Lin, Mingjie, Wang, Jun, Turgut, Damla, University of Central Florida
Abstract / Description
Contemporary reconfigurable hardware devices have the capability to achieve high performance, powerefficiency, and adaptability required to meet a wide range of design goals. With scaling challenges facing current complementary metal oxide semiconductor (CMOS), new concepts and methodologies supportingefficient adaptation to handle reliability issues are becoming increasingly prominent. Reconfigurable hardware and their ability to realize self-organization features are expected to play a key...
Show moreContemporary reconfigurable hardware devices have the capability to achieve high performance, powerefficiency, and adaptability required to meet a wide range of design goals. With scaling challenges facing current complementary metal oxide semiconductor (CMOS), new concepts and methodologies supportingefficient adaptation to handle reliability issues are becoming increasingly prominent. Reconfigurable hardware and their ability to realize self-organization features are expected to play a key role in designingfuture dependable hardware architectures. However, the exponential increase in density and complexity of current commercial SRAM-based field-programmable gate arrays (FPGAs) has escalated the overheadassociated with dynamic runtime design adaptation. Traditionally, static modular redundancy techniques areconsidered to surmount this limitation; however, they can incur substantial overheads in both area andpower requirements. To achieve a better trade-off among performance, area, power, and reliability, thisresearch proposes design-time approaches that enable fine selection of redundancy level based on target reliability goals and autonomous adaptation to runtime demands. To achieve this goal, three studies were conducted:First, a graph and set theoretic approach, named Hypergraph-Cover Diversity (HCD), is introduced as a preemptive design technique to shift the dominant costs of resiliency to design-time. In particular, union-freehypergraphs are exploited to partition the reconfigurable resources pool into highly separable subsets ofresources, each of which can be utilized by the same synthesized application netlist. The diverseimplementations provide reconfiguration-based resilience throughout the system lifetime while avoiding thesignificant overheads associated with runtime placement and routing phases. Evaluation on a Motion-JPEGimage compression core using a Xilinx 7-series-based FPGA hardware platform has demonstrated thepotential of the proposed FT method to achieve 37.5% area saving and up to 66% reduction in powerconsumption compared to the frequently-used TMR scheme while providing superior fault tolerance.Second, Design Disjunction based on non-adaptive group testing is developed to realize a low-overheadfault tolerant system capable of handling self-testing and self-recovery using runtime partial reconfiguration.Reconfiguration is guided by resource grouping procedures which employ non-linear measurements given by the constructive property of f-disjunctness to extend runtime resilience to a large fault space and realize a favorable range of tradeoffs. Disjunct designs are created using the mosaic convergence algorithmdeveloped such that at least one configuration in the library evades any occurrence of up to d resource faults, where d is lower-bounded by f. Experimental results for a set of MCNC and ISCAS benchmarks havedemonstrated f-diagnosability at the individual slice level with average isolation resolution of 96.4% (94.4%) for f=1 (f=2) while incurring an average critical path delay impact of only 1.49% and area cost roughly comparable to conventional 2-MR approaches. Finally, the proposed Design Disjunction method is evaluated as a design-time method to improve timing yield in the presence of large random within-die (WID) process variations for application with a moderately high production capacity.
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Date Issued
2015
Identifier
CFE0006250, ucf:51086
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006250
Zora
Title
Zora.
Creator
Tyrrell, Genevieve, Roney, Lisa, Rushin, Patrick, Scott, John, University of Central Florida
Abstract / Description
This mixed-media memoir uses a variety of forms from short epigrammatic essays to straightforward stories and graphic narratives to explore the author's coming-of-age experiences augmented by chronic illness. Trying to succeed in the film industry, romance, and family situations, the young female narrator navigates the often unexpected or disappointing consequences of having an autonomic nervous system disorder. Relationships between conflicting identities emerge(-)between healthy versus sick...
Show moreThis mixed-media memoir uses a variety of forms from short epigrammatic essays to straightforward stories and graphic narratives to explore the author's coming-of-age experiences augmented by chronic illness. Trying to succeed in the film industry, romance, and family situations, the young female narrator navigates the often unexpected or disappointing consequences of having an autonomic nervous system disorder. Relationships between conflicting identities emerge(-)between healthy versus sick self, projected/envisioned versus actual self, and tough versus vulnerable self(-)as the narrator journeys toward a more complete and accepting self-understanding.
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Date Issued
2013
Identifier
CFE0004763, ucf:49777
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0004763
Autonomous Recovery of Reconfigurable Logic Devices using Priority Escalation of Slack
Title
Autonomous Recovery of Reconfigurable Logic Devices using Priority Escalation of Slack.
Creator
Imran, Syednaveed, DeMara, Ronald, Mikhael, Wasfy, Lin, Mingjie, Yuan, Jiann-Shiun, Geiger, Christopher, University of Central Florida
Abstract / Description
Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases.To extend these concepts to semiconductor aging and process variation in the deep...
Show moreField Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases.To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Reconfigurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric.FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria.
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Date Issued
2013
Identifier
CFE0005006, ucf:50005
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0005006