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(1 - 5 of 5)
- Title
- TRANSIENT RESPONSE IMPROVEMENT FOR MULTI-PHASE VOLTAGE REGULATORS.
- Creator
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Xiao, Shangyang, Batarseh, Issa, University of Central Florida
- Abstract / Description
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Next generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew...
Show moreNext generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew rate of the transient current can be as high as 1.9A/ns [1, 2]. Meanwhile, the transient-response requirements are becoming stringer and stringer. This dissertation presents several topics on how to improve transient response for multi-phase voltage regulators. The Adaptive Modulation Control (AMC) is a type of non-linear control method which has proven to be effective in achieving high bandwidth designs as well as stabilizing the control loop during large load transients. It adaptively adjusts control bandwidth by changing the modulation gain, depending on different load conditions. With the AMC, a multiphase voltage regulator can be designed with an aggressively high bandwidth. When in heavy load transients where the loop could be potentially unstable, the bandwidth is lowered. Therefore, the AMC provides an optimal means for robust high-bandwidth design with excellent transient performance. The Error Amplifier Voltage Positioning (EAVP) is proposed to improve transient response by removing undesired spikes and dips after initial transient response. The EAVP works only in a short period of time during transient events without modifying the power stage and changing the control loop gain. It facilitates the error amplifier voltage recovering during transient events, achieving a fast settling time without impact on the whole control loop. Coupled inductors are an emerging topology for computing power supplies as VRs with coupled inductors show dynamic and steady-state advantages over traditional VRs. This dissertation first covers the coupling mechanism in terms of both electrical and reluctance modeling. Since the magnetizing inductance plays an important role in the coupled-inductor operation, a unified State-Space Averaging model is then built for a two-phase coupled-inductor voltage regulator. The DC solutions of the phase currents are derived in order to show the impact of the magnetizing inductance on phase current balancing. A small signal model is obtained based on the state-space-averaging model. The effects of magnetizing inductance on dynamic performance are presented. The limitations of conventional DCR current-sensing for coupled inductors are addressed. Traditional inductor DCR current sensing topology and prior arts fail to extract phase currents for coupled inductors. Two new DCR current sensing topologies for coupled inductors are presented in this dissertation. By implementation of simple RC networks, the proposed topologies can preserve the coupling effect between phases. As a result, accurate phase inductor currents and total current can be sensed, resulting in excellent current and voltage regulation. While coupled-inductor topologies are showing advantages in transient response and are becoming industry practices, they are suffering from low steady-state operating efficiency. Motivated by the challenging transient and efficiency requirements, this dissertation proposes a Full Bridge Coupled Inductor (FBCI) scheme which is able to improve transient response as well as savor high efficiency at (a) steady state. The FBCI can change the circuit configuration under different operational conditions. Its "flexible" topology is able to optimize both transient response and steady-state efficiency. The flexible core configuration makes implementation easy and clear of IP issues. A novel design methodology for planar magnetics based on numerical analysis of electromagnetic fields is offered and successfully applied to the design of low-voltage high power density dc-dc converters. The design methodology features intense use of FEM simulation. The design issues of planar magnetics, including loss mechanism in copper and core, winding design on PCB, core selections, winding arrangements and so on are first reviewed. After that, FEM simulators are introduced to numerically compute the core loss and winding loss. Consequently, a software platform for magnetics design is established, and optimized magnetics can then be achieved. Dynamic voltage scaling (DVS) technology is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this dissertation, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme.
Show less - Date Issued
- 2008
- Identifier
- CFE0002397, ucf:47738
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002397
- Title
- HIGH SLEW RATE HIGH-EFFICIENCY DC-DC CONVERTER.
- Creator
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Wang, Xiangcheng, Issa, Batarseh, University of Central Florida
- Abstract / Description
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Active transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive...
Show moreActive transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive nonlinear control has been proposed to reduce delay times in the actual controller, which injects one nonlinear signal in transient periods and simplifies the linear controller design. Switching mode current compensator with nonlinear control in secondary side is proposed to eliminate the effect of opotocoupler, which reduces response times and simplifies the linear controller design in isolated DC-DC converters. A novel control method has been carried out in two-stage isolated DC-DC converter to simplify the control scheme and improve the transient response, allowing for high duty cycle operation and large step-down voltage ratio with high efficiency. A balancing winding network composed of small power rating components is used to mitigate the double pole-zero effect in complementary-controlled isolated DC-DC converter, which simplifies the linear control design and improves the transient response without delay time. A parallel post regulator (PPR) is proposed for wide range input isolated DC-DC converter with secondary side control, which provides small part of output power and most of them are handled by unregulated rectifier with high efficiency. PPR is easy to achieve ZVS in primary side both in wide range input and full load range due to 0.5 duty cycle. PPR has reduced conduction loss and reduced voltage rating in the secondary side due to high turn ratio transformer, resulting in up to 8 percent efficiency improvement in the prototype compared to conventional methods.
Show less - Date Issued
- 2006
- Identifier
- CFE0001123, ucf:46877
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001123
- Title
- Anthropogenic Organic Chemical Removal from a Surficial Groundwater and Mass Transfer Modeling in a Nanofiltration Membrane Process.
- Creator
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Jeffery, Samantha, Duranceau, Steven, Lee, Woo Hyoung, Sadmani, A H M Anwar, Yestrebsky, Cherie, University of Central Florida
- Abstract / Description
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This dissertation reports on research related to trace organic compounds (TrOCs) in surficial groundwater supplies and their subsequent removal from nanofiltration (NF) membranes. The research was conducted along coastal South Florida in cooperation with the Town of Jupiter Water Utilities, Jupiter, FL (Town). The focus of the research was to determine the extent of reclaimed water impacts on surficial groundwater supplies and subsequent effects on the Town's NF water treatment plant. Routine...
Show moreThis dissertation reports on research related to trace organic compounds (TrOCs) in surficial groundwater supplies and their subsequent removal from nanofiltration (NF) membranes. The research was conducted along coastal South Florida in cooperation with the Town of Jupiter Water Utilities, Jupiter, FL (Town). The focus of the research was to determine the extent of reclaimed water impacts on surficial groundwater supplies and subsequent effects on the Town's NF water treatment plant. Routine monitoring of fourteen TrOCs in reclaimed water and at the water treatment facility revealed varying degrees of TrOC detection in the environment. Certain TrOCs, including caffeine and DEET, were detected in a majority of the water sampling locations evaluated in this work. However, subsequent dilution with highly-treated reverse osmosis (RO) permeate from alternative supplies resulted in TrOCs below detection limits in potable water at the point-of-entry (POE). Pilot testing was employed to determine the extent of TrOC removal by NF. Prior to evaluating TrOC removal, hydraulic transients within the pilot process were first examined to determine the required length of time the pilot needed to reach steady-state. The transient response of a center-port NF membrane process was evaluated using a step-input dose of a sodium chloride solution. The pilot was configured as a two-stage, split-feed, center-exit, 7:2 pressure vessel array process, where the feed water is fed to both ends of six element pressure vessels, and permeate and concentrate streams are collected after only three membrane elements. The transient response was described as a log-logistic system with a maximum delay time of 285 seconds for an 85% water recovery and 267 gallon per minute feed flowrate.Eleven TrOC pilot unit experiments were conducted with feed concentrations ranging from 0.52 to 4,500 ?g/L. TrOC rejection was well-correlated with compound molecular volume and polarizability, with coefficient of determination (R2) values of 0.94. To enhance this correlation, an extensive literature review was conducted and independent literature sources were correlated with rejection. Literature citations reporting the removal effectiveness of an additional sixty-one TrOCs by loose NF membranes (a total of 95 data points) were found to be well-correlated with molecular volume and polarizability, with R2 values of 0.72 and 0.71, respectively.Of the TrOC's detected during this research, the anthropogenic solute caffeine was selected to be modeled using the homogeneous solution diffusion model (HSDM) and the HSDM with film theory (HSDM-FT). Mass transfer coefficients, K_w (water) K_s (caffeine), and k_b (caffeine back-transport) were determined experimentally, and K_s was also determined using the Sherwood correlation method. Findings indicate that caffeine transport through the NF pilot could be explained using experimentally determined K_s values without incorporating film theory, since the HSDM resulted in a better correlation between predicted and actual caffeine permeate concentrations compared to the HSDM-FT and the HSDM using K_s obtained using Sherwood applications. Predicted versus actual caffeine content was linearly compared, revealing R2 values on the order of 0.99, 0.96, and 0.99 for the HSDM without FT, HSDM-FT, and HSDM using a K_s value obtained using the Sherwood correlation method. However, the use of the HSDM-FT and the Sherwood number resulted in the over-prediction of caffeine concentrations in permeate streams by 27 percent and 104 percent, respectively.
Show less - Date Issued
- 2016
- Identifier
- CFE0006331, ucf:51545
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006331
- Title
- HIGH CURRENT DENSITY LOW VOLTAGE ISOLATED DC-DC CONVERTERSWITH FAST TRANSIENT RESPONSE.
- Creator
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Yao, Liangbin, Batarseh, Issa, University of Central Florida
- Abstract / Description
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With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current...
Show moreWith the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.
Show less - Date Issued
- 2007
- Identifier
- CFE0001814, ucf:47336
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001814
- Title
- Transient and Distributed Algorithms to Improve Islanding Detection Capability of Inverter Based Distributed Generation.
- Creator
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Alhosani, Mohamed, Qu, Zhihua, Mikhael, Wasfy, Haralambous, Michael, Behal, Aman, Xu, Chengying, University of Central Florida
- Abstract / Description
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Recently, a lot of research work has been dedicated toward enhancing performance, reliability and integrity of distributed energy resources that are integrated into distribution networks. The problem of islanding detection and islanding prevention (i.e. anti-islanding) has stimulated a lot of research due to its role in severely compromising the safety of working personnel and resulting in equipment damages. Various Islanding Detection Methods (IDMs) have been developed within the last ten...
Show moreRecently, a lot of research work has been dedicated toward enhancing performance, reliability and integrity of distributed energy resources that are integrated into distribution networks. The problem of islanding detection and islanding prevention (i.e. anti-islanding) has stimulated a lot of research due to its role in severely compromising the safety of working personnel and resulting in equipment damages. Various Islanding Detection Methods (IDMs) have been developed within the last ten years in anticipation of the tremendous increase in the penetration of Distributed Generation (DG) in distribution system. This work proposes new IDMs that rely on transient and distributed behaviors to improve integrity and performance of DGs while maintaining multi-DG islanding detection capability.In this thesis, the following questions have been addressed: How to utilize the transient behavior arising from an islanding condition to improve detectability and robust performance of IDMs in a distributive manner? How to reduce the negative stability impact of the well-known Sandia Frequency Shift (SFS) IDM while maintaining its islanding detection capability? How to incorporate the perturbations provided by each of DGs in such a way that the negative interference of different IDMs is minimized without the need of any type of communication among the different DGs?It is shown that the proposed techniques are local, scalable and robust against different loading conditions and topology changes. Also, the proposed techniques can successfully distinguish an islanding condition from other disturbances that may occur in power system networks. This work improves the efficiency, reliability and safety of integrated DGs, which presents a necessary advance toward making electric power grids a smart grid.
Show less - Date Issued
- 2013
- Identifier
- CFE0005295, ucf:50567
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0005295
