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NEGATIVE BIAS TEMPERATURE INSTABILITY AND CHARGE TRAPPING EFFECTS ON ANALOG AND DIGITAL CIRCUIT RELIABILITY

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Date Issued:
2007
Abstract/Description:
Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.
Title: NEGATIVE BIAS TEMPERATURE INSTABILITY AND CHARGE TRAPPING EFFECTS ON ANALOG AND DIGITAL CIRCUIT RELIABILITY.
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Name(s): Yu, Yixin, Author
Yuan, Jiann. S., Committee Chair
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2007
Publisher: University of Central Florida
Language(s): English
Abstract/Description: Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.
Identifier: CFE0001930 (IID), ucf:47432 (fedora)
Note(s): 2007-12-01
M.S.E.E.
Engineering and Computer Science, School of Electrical Engineering and Computer Science
Masters
This record was generated from author submitted information.
Subject(s): NBTI
Charge trapping
current mirror
operation amplifier
inverter
ring oscillator
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0001930
Restrictions on Access: public
Host Institution: UCF

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