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CONTROLLED ASSEMBLY AND ELECTRONIC TRANSPORT STUDIES OF SOLUTION PROCESSED CARBON NANOTUBE DEVICES

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Date Issued:
2010
Abstract/Description:
Developing techniques for the parallel fabrication of Complementary Metal Oxide Semiconductor (CMOS) compatible single walled carbon nanotube (SWNT) electronic devices is of great importance for nanoelectronic applications. In this thesis, solution processed SWNTs in combination with AC dielectrophoresis (DEP) were utilized to fabricate CMOS compatible SWNT field effect transistors (FETs) and single electron transistors (SETs) with high yield and their detailed electronic transport properties were studied. Solution processing of SWNTs is attractive not only for the high throughput and parallel manufacturing of SWNT devices but also due to the ease of processing at room temperature, and compatibility with various substrates. However, it is generally believed that solution processing introduces defects and can degrade electronic transport properties. The results presented in this dissertation show that devices assembled from stable solutions of SWNT can give rise to high quality FET devices at room temperature and relatively clean SET behavior at low temperature. This is a strong indication that there are no or few intrinsic defects in the SWNTs. The dissertation will also discuss the controlled fabrication of size tunable SWNT SET devices using a novel mechanical template approach which offers a route towards the parallel fabrication of room temperature SET devices. The approach is based on the formation of two tunnel barriers created in a SWNT a distance L apart by bending the SWNT at the edge of a local Al/Al2O3 bottom gate. The local gate tunes individual electrons one by one in the device and defines the size of the quantum dot though its width. By tuning both the back gate and local gate, it is possible to tune the transparency of tunnel barriers and the size of the quantum dot further. Detailed transport spectroscopy of these devices will be presented.
Title: CONTROLLED ASSEMBLY AND ELECTRONIC TRANSPORT STUDIES OF SOLUTION PROCESSED CARBON NANOTUBE DEVICES.
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Name(s): Stokes, Paul, Author
Khondaker, Saiful I., Committee Chair
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2010
Publisher: University of Central Florida
Language(s): English
Abstract/Description: Developing techniques for the parallel fabrication of Complementary Metal Oxide Semiconductor (CMOS) compatible single walled carbon nanotube (SWNT) electronic devices is of great importance for nanoelectronic applications. In this thesis, solution processed SWNTs in combination with AC dielectrophoresis (DEP) were utilized to fabricate CMOS compatible SWNT field effect transistors (FETs) and single electron transistors (SETs) with high yield and their detailed electronic transport properties were studied. Solution processing of SWNTs is attractive not only for the high throughput and parallel manufacturing of SWNT devices but also due to the ease of processing at room temperature, and compatibility with various substrates. However, it is generally believed that solution processing introduces defects and can degrade electronic transport properties. The results presented in this dissertation show that devices assembled from stable solutions of SWNT can give rise to high quality FET devices at room temperature and relatively clean SET behavior at low temperature. This is a strong indication that there are no or few intrinsic defects in the SWNTs. The dissertation will also discuss the controlled fabrication of size tunable SWNT SET devices using a novel mechanical template approach which offers a route towards the parallel fabrication of room temperature SET devices. The approach is based on the formation of two tunnel barriers created in a SWNT a distance L apart by bending the SWNT at the edge of a local Al/Al2O3 bottom gate. The local gate tunes individual electrons one by one in the device and defines the size of the quantum dot though its width. By tuning both the back gate and local gate, it is possible to tune the transparency of tunnel barriers and the size of the quantum dot further. Detailed transport spectroscopy of these devices will be presented.
Identifier: CFE0003061 (IID), ucf:48310 (fedora)
Note(s): 2010-05-01
Ph.D.
Sciences, Department of Physics
Doctorate
This record was generated from author submitted information.
Subject(s): nanotube
dielectrophoresis
solution processed
electron transport
assembly
nanoelectronics
single electron transistor
quantum dot
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0003061
Restrictions on Access: private 2013-04-01
Host Institution: UCF

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