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CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT

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Date Issued:
2011
Abstract/Description:
This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18[micro]m CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
Title: CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT.
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Name(s): Skaria, Giji, Author
Yuan, Jiann, Committee Chair
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2011
Publisher: University of Central Florida
Language(s): English
Abstract/Description: This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18[micro]m CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
Identifier: CFE0004030 (IID), ucf:49161 (fedora)
Note(s): 2011-08-01
M.S.E.E.
Engineering and Computer Science, School of Electrical Engineering and Computer Science
Masters
This record was generated from author submitted information.
Subject(s): 0.18[micro]m
CMOS
Class F
Cascode-Class F
Gate-Drain Resistance
Inverse-class F
Power Amplifier
Reliability
Stress.
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0004030
Restrictions on Access: public
Host Institution: UCF

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