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Transient Safe Operating Area (TSOA) for ESD applications

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Date Issued:
2012
Abstract/Description:
A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD).A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins.The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs.The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identified.
Title: Transient Safe Operating Area (TSOA) for ESD applications.
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Name(s): Malobabic, Slavica, Author
Liou, Juin, Committee Chair
Shen, Zheng, Committee Member
Yuan, Jiann-Shiun, Committee Member
Vinson, James, Committee Member
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2012
Publisher: University of Central Florida
Language(s): English
Abstract/Description: A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD).A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins.The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs.The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identified.
Identifier: CFE0004405 (IID), ucf:49363 (fedora)
Note(s): 2012-08-01
Ph.D.
Engineering and Computer Science, Electrical Engineering and Computer Science
Doctoral
This record was generated from author submitted information.
Subject(s): ESD -- HMM -- IEC -- Gate Oxide -- TCAD -- TLP -- SCR
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0004405
Restrictions on Access: public 2012-08-15
Host Institution: UCF

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