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Assessing Approximate Arithmetic Designs in the presence of Process Variations and Voltage Scaling

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Date Issued:
2015
Abstract/Description:
As environmental concerns and portability of electronic devices move to the forefront of priorities,innovative approaches which reduce processor energy consumption are sought. Approximatearithmetic units are one of the avenues whereby significant energy savings can be achieved. Approximationof fundamental arithmetic units is achieved by judiciously reducing the number oftransistors in the circuit. A satisfactory tradeoff of energy vs. accuracy of the circuit can be determinedby trial-and-error methods of each functional approximation. Although the accuracy of theoutput is compromised, it is only decreased to an acceptable extent that can still fulfill processingrequirements.A number of scenarios are evaluated with approximate arithmetic units to thoroughly cross-checkthem with their accurate counterparts. Some of the attributes evaluated are energy consumption,delay and process variation. Additionally, novel methods to create such approximate unitsare developed. One such method developed uses a Genetic Algorithm (GA), which mimics thebiologically-inspired evolutionary techniques to obtain an optimal solution. A GA employs geneticoperators such as crossover and mutation to mix and match several different types of approximateadders to find the best possible combination of such units for a given input set. As the GA usuallyconsumes a significant amount of time as the size of the input set increases, we tackled this problemby using various methods to parallelize the fitness computation process of the GA, which isthe most compute intensive task. The parallelization improved the computation time from 2,250seconds to 1,370 seconds for up to 8 threads, using both OpenMP and Intel TBB. Apart from usingthe GA with seeded multiple approximate units, other seeds such as basic logic gates with limitedlogic space were used to develop completely new multi-bit approximate adders with good fitnesslevels.iiiThe effect of process variation was also calculated. As the number of transistors is reduced, thedistribution of the transistor widths and gate oxide may shift away from a Gaussian Curve. This resultwas demonstrated in different types of single-bit adders with the delay sigma increasing from6psec to 12psec, and when the voltage is scaled to Near-Threshold-Voltage (NTV) levels sigmaincreases by up to 5psec. Approximate Arithmetic Units were not affected greatly by the changein distribution of the thickness of the gate oxide. Even when considering the 3-sigma value, thedelay of an approximate adder remains below that of a precise adder with additional transistors.Additionally, it is demonstrated that the GA obtains innovative solutions to the appropriate combinationof approximate arithmetic units, to achieve a good balance between energy savings andaccuracy.
Title: Assessing Approximate Arithmetic Designs in the presence of Process Variations and Voltage Scaling.
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Name(s): Naseer, Adnan Aquib, Author
DeMara, Ronald, Committee Chair
Lin, Mingjie, Committee Member
Karwowski, Waldemar, Committee Member
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2015
Publisher: University of Central Florida
Language(s): English
Abstract/Description: As environmental concerns and portability of electronic devices move to the forefront of priorities,innovative approaches which reduce processor energy consumption are sought. Approximatearithmetic units are one of the avenues whereby significant energy savings can be achieved. Approximationof fundamental arithmetic units is achieved by judiciously reducing the number oftransistors in the circuit. A satisfactory tradeoff of energy vs. accuracy of the circuit can be determinedby trial-and-error methods of each functional approximation. Although the accuracy of theoutput is compromised, it is only decreased to an acceptable extent that can still fulfill processingrequirements.A number of scenarios are evaluated with approximate arithmetic units to thoroughly cross-checkthem with their accurate counterparts. Some of the attributes evaluated are energy consumption,delay and process variation. Additionally, novel methods to create such approximate unitsare developed. One such method developed uses a Genetic Algorithm (GA), which mimics thebiologically-inspired evolutionary techniques to obtain an optimal solution. A GA employs geneticoperators such as crossover and mutation to mix and match several different types of approximateadders to find the best possible combination of such units for a given input set. As the GA usuallyconsumes a significant amount of time as the size of the input set increases, we tackled this problemby using various methods to parallelize the fitness computation process of the GA, which isthe most compute intensive task. The parallelization improved the computation time from 2,250seconds to 1,370 seconds for up to 8 threads, using both OpenMP and Intel TBB. Apart from usingthe GA with seeded multiple approximate units, other seeds such as basic logic gates with limitedlogic space were used to develop completely new multi-bit approximate adders with good fitnesslevels.iiiThe effect of process variation was also calculated. As the number of transistors is reduced, thedistribution of the transistor widths and gate oxide may shift away from a Gaussian Curve. This resultwas demonstrated in different types of single-bit adders with the delay sigma increasing from6psec to 12psec, and when the voltage is scaled to Near-Threshold-Voltage (NTV) levels sigmaincreases by up to 5psec. Approximate Arithmetic Units were not affected greatly by the changein distribution of the thickness of the gate oxide. Even when considering the 3-sigma value, thedelay of an approximate adder remains below that of a precise adder with additional transistors.Additionally, it is demonstrated that the GA obtains innovative solutions to the appropriate combinationof approximate arithmetic units, to achieve a good balance between energy savings andaccuracy.
Identifier: CFE0005675 (IID), ucf:50165 (fedora)
Note(s): 2015-05-01
M.S.Cp.E.
Engineering and Computer Science, Electrical Engineering and Computer Science
Masters
This record was generated from author submitted information.
Subject(s): Adders Approximate
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0005675
Restrictions on Access: public 2015-05-15
Host Institution: UCF

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