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Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters
| Title: | Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters. |
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| Name(s): |
Parkey, Charna, Author Mikhael, Wasfy, Committee Chair Qu, Zhihua, Committee Member Georgiopoulos, Michael, Committee Member Myers, Brent, Committee Member Wei, Lei, Committee Member Chester, David, Committee Member University of Central Florida, Degree Grantor |
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| Type of Resource: | text | |
| Date Issued: | 2015 | |
| Publisher: | University of Central Florida | |
| Language(s): | English | |
| Abstract/Description: | Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation. | |
| Identifier: | CFE0005683 (IID), ucf:50171 (fedora) | |
| Note(s): |
2015-05-01 Ph.D. Engineering and Computer Science, Electrical Engineering and Computer Science Doctoral This record was generated from author submitted information. |
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| Subject(s): | adaptive filter -- time interleaved -- analog to digital converter -- TIADC | |
| Persistent Link to This Record: | http://purl.flvc.org/ucf/fd/CFE0005683 | |
| Restrictions on Access: | public 2015-05-15 | |
| Host Institution: | UCF |
