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Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation
| Title: | Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation. |
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| Name(s): |
Mendoza Macias, Raul, Author Yuan, Jiann-Shiun, Committee Chair Sundaram, Kalpathy, Committee Member Fan, Deliang, Committee Member University of Central Florida, Degree Grantor |
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| Type of Resource: | text | |
| Date Issued: | 2016 | |
| Publisher: | University of Central Florida | |
| Language(s): | English | |
| Abstract/Description: | Vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In addition, electrical parameters such as threshold voltage and charge balance are also examined. Increasing the superjunction doping in the drift region of VDMOS reduces the on-resistance by 26%, while maintaining the same breakdown voltage and threshold voltage compared to that of the conventional VDMOS power transistor with similar device design without using a superjunction. | |
| Identifier: | CFE0006354 (IID), ucf:51525 (fedora) | |
| Note(s): |
2016-08-01 M.S.E.E. Engineering and Computer Science, Electrical Engineering and Computer Engineering Masters This record was generated from author submitted information. |
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| Subject(s): | VDMOS -- superjunction -- simulation -- breakdown voltage -- on-resistance | |
| Persistent Link to This Record: | http://purl.flvc.org/ucf/fd/CFE0006354 | |
| Restrictions on Access: | public 2016-08-15 | |
| Host Institution: | UCF |
