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LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation

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Date Issued:
2017
Abstract/Description:
The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance (&)#215; gate charge) of 5.93 m?-nC.
Title: LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation.
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Name(s): Salih, Aiman, Author
Yuan, Jiann-Shiun, Committee Chair
Sundaram, Kalpathy, Committee Member
Kapoor, Vikram, Committee Member
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2017
Publisher: University of Central Florida
Language(s): English
Abstract/Description: The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance (&)#215; gate charge) of 5.93 m?-nC.
Identifier: CFE0006955 (IID), ucf:51673 (fedora)
Note(s): 2017-05-01
M.S.E.E.
Engineering and Computer Science, Electrical Engineering and Computer Engineering
Masters
This record was generated from author submitted information.
Subject(s): Data center power efficiency improvement -- Electric vehicle power management -- LDMOS -- Power devices -- Low voltage device -- Super-junction -- TCAD simulation
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0006955
Restrictions on Access: campus 2018-11-15
Host Institution: UCF

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