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Normally-Off Computing Design Methodology Using Spintronics: from Devices to Architectures
| Title: | Normally-Off Computing Design Methodology Using Spintronics: from Devices to Architectures. |
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| Name(s): |
Roohi, Arman, Author DeMara, Ronald, Committee Chair Abdolvand, Reza, Committee Member Wang, Jun, Committee Member Fan, Deliang, Committee Member Del Barco, Enrique, Committee Member University of Central Florida, Degree Grantor |
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| Type of Resource: | text | |
| Date Issued: | 2019 | |
| Publisher: | University of Central Florida | |
| Language(s): | English | |
| Abstract/Description: | Energy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle-variable computing approach leveraging the non-volatility inherent in post-CMOS switching devices. The foundations of EIC will be advanced from the ground up by extending Spin Hall Effect Magnetic Tunnel Junction (SHE-MTJ) device models to realize SHE-MTJ-based Majority Gate (MG) and Polymorphic Gate (PG) logic approaches and libraries, that leverage intrinsic-non-volatility to realize middleware-coherent, intermittent computation without checkpointing, micro-tasking, or software bloat and energy overheads vital to IoT. Device-level EIC research concentrates on encapsulating SHE-MTJ behavior with a compact model to leverage the non-volatility of the device for intrinsic provision of intermittent computation and lifetime energy reduction. Based on this model, the circuit-level EIC contributions will entail the design, simulation, and analysis of PG-based spintronic logic which is adaptable at the gate-level to support variable duty cycle execution that is robust to brief and extended supply outages or unscheduled dropouts, and development of spin-based research synthesis and optimization routines compatible with existing commercial toolchains. These tools will be employed to design a hybrid post-CMOS processing unit utilizing pipelining and power-gating through state-holding properties within the datapath itself, thus eliminating checkpointing and data transfer operations. | |
| Identifier: | CFE0007526 (IID), ucf:52619 (fedora) | |
| Note(s): |
2019-05-01 Ph.D. Engineering and Computer Science, Electrical Engineering and Computer Engineering Doctoral This record was generated from author submitted information. |
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| Subject(s): | Low-power computation -- normally-off computating -- logic-in-memory architecture -- non-volatile logic -- spin-transfer torque switching -- magnetic tunnel junction | |
| Persistent Link to This Record: | http://purl.flvc.org/ucf/fd/CFE0007526 | |
| Restrictions on Access: | campus 2020-05-15 | |
| Host Institution: | UCF |
