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DESIGN AND IMPLEMENTATION OF A HARDWARE LEVEL CONTENT NETWORKING FRONT END DEVICE
- Date Issued:
- 2007
- Abstract/Description:
- The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This thesis proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA.
Title: | DESIGN AND IMPLEMENTATION OF A HARDWARE LEVEL CONTENT NETWORKING FRONT END DEVICE. |
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Name(s): |
Buboltz, Jeremy, Author Kocak, Taskin, Committee Chair University of Central Florida, Degree Grantor |
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Type of Resource: | text | |
Date Issued: | 2007 | |
Publisher: | University of Central Florida | |
Language(s): | English | |
Abstract/Description: | The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This thesis proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA. | |
Identifier: | CFE0001888 (IID), ucf:47390 (fedora) | |
Note(s): |
2007-12-01 M.S.Cp.E. Engineering and Computer Science, School of Electrical Engineering and Computer Science Masters This record was generated from author submitted information. |
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Subject(s): |
Content Networking Front End Device Hardware Implementation |
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Persistent Link to This Record: | http://purl.flvc.org/ucf/fd/CFE0001888 | |
Restrictions on Access: | campus 2008-12-04 | |
Host Institution: | UCF |