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The Performance and Power Impact of Using Multiple DRAM Address Mapping Schemes in Multicore Processors

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Date Issued:
2011
Abstract/Description:
Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications' performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing un-accessed devices to be put into power-down mode, hence saving power to meet a certain power budget.
Title: The Performance and Power Impact of Using Multiple DRAM Address Mapping Schemes in Multicore Processors.
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Name(s): Jadaa, Rami, Author
Heinrich, Mark, Committee Chair
DeMara, Ronald, Committee Member
Yuan, Jiann-Shiun, Committee Member
, Committee Member
University of Central Florida, Degree Grantor
Type of Resource: text
Date Issued: 2011
Publisher: University of Central Florida
Language(s): English
Abstract/Description: Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications' performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing un-accessed devices to be put into power-down mode, hence saving power to meet a certain power budget.
Identifier: CFE0004121 (IID), ucf:49118 (fedora)
Note(s): 2011-12-01
M.S.E.E.
Engineering and Computer Science, Electrical Engineering and Computer Science
Masters
This record was generated from author submitted information.
Subject(s): DRAM -- DDR3 -- Memory Controller -- Memory Level Parallelism -- Memory Throttling -- Dynamic Address Mapping Scheme -- Physical Address Translation -- Bandwidth -- Energy per Operation -- Synthetic Memory Traces
Persistent Link to This Record: http://purl.flvc.org/ucf/fd/CFE0004121
Restrictions on Access: public 2011-12-15
Host Institution: UCF

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