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Pages
- Title
- RF Energy Harvesting for Implantable ICs with On-chip Antenna.
- Creator
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Liu, Yu-chun, Yuan, Jiann-Shiun, Gong, Xun, Jones, W, University of Central Florida
- Abstract / Description
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Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite...
Show moreNowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1(&)#215;1(&)#215;2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.
Show less - Date Issued
- 2014
- Identifier
- CFE0005202, ucf:50652
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0005202
- Title
- Chemical Vapor Deposition Growth of Large Area 2D MoS2 Layers: Layer Orientation Control, Heterostructure Integration, And Applications for Stretchable Sensors.
- Creator
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Islam, Md. Ashraful, Jung, YeonWoong, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Roy, Tania, Cho, Hyoung Jin, University of Central Florida
- Abstract / Description
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Two-dimensional (2D)-layered MoS2 layers have exhibited a broad set of unusual and superior material properties unattainable in any traditional bulk materials, drawing significant research interests nowadays. For instance, they present excellent semiconducting properties accompanying high carrier mobility and large current ON/OFF ratio as well as extensive in-plane strain limit and thickness, projecting high suitably for emerging flexible and stretchable electronics. Such properties and...
Show moreTwo-dimensional (2D)-layered MoS2 layers have exhibited a broad set of unusual and superior material properties unattainable in any traditional bulk materials, drawing significant research interests nowadays. For instance, they present excellent semiconducting properties accompanying high carrier mobility and large current ON/OFF ratio as well as extensive in-plane strain limit and thickness, projecting high suitably for emerging flexible and stretchable electronics. Such properties and applications strongly depend on the physical orientation and chemical composition of constituent 2D layers. 2D MoS2 layers chemically grown in two distinct orientations, e.g., horizontal alignment for electronics and optoelectronics, and vertical alignment for electrochemical and sensing applications. Moreover, 2D heterostructure layers composed of vertically stacked dissimilar 2D TMDs held via weak van der Waals (vdW) attractions offer unique 2D/2D interfaces, envisioned to display exotic material properties, unattainable in their monocomponent counterparts. However, the underlying principle of their layer orientation-controlled growth and integrations are not well suited for scalable production, leaving their projected technological opportunities far from being realized for various novel applications. Herein, I study various aspects of 2D MoS2 layers that were studied from their large-area layer-orientation controlled growth and heterostructures integration to applications in stretchable electronic devices. I developed a chemical vapor deposition (CVD) synthesis, which can grow large-area ((>) cm2) 2D MoS2 layers in a layer-controlled manner and investigated their underlying growth mechanism. I then developed a viable transfer approach of the as-grown 2D layers and integrated them into secondary target substrates to realize a new type of 2D MoS2-layers based heterostructures. To further extend their layer-controlled CVD growth and integration approach, a high-performance stretchable 2D MoS2-based electrical sensors were demonstrated on the elastomeric substrates with unconventional structural layouts. This study paves the way to explore this emerging atomically-thin material in realizing a wide range of unusual device and technologies which have been foreseen to be impossible otherwise.
Show less - Date Issued
- 2019
- Identifier
- CFE0007820, ucf:52812
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007820
- Title
- Study of Novel Power Semiconductor Devices for Performance and Reliability.
- Creator
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Padmanabhan, Karthik, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Atia, George, DeMara, Ronald, Chow, Lee, University of Central Florida
- Abstract / Description
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Power Semiconductor Devices are crucial components in present day power electronic systems. The performance and efficiency of the devices have a direct correlation with the power system efficiency. This dissertation will examine some of the components that are commonly used in a power system, with emphasis on their performance characteristics and reliability. In recent times, there has a proliferation of charge balance devices in high voltage discrete power devices. We examine the same charge...
Show morePower Semiconductor Devices are crucial components in present day power electronic systems. The performance and efficiency of the devices have a direct correlation with the power system efficiency. This dissertation will examine some of the components that are commonly used in a power system, with emphasis on their performance characteristics and reliability. In recent times, there has a proliferation of charge balance devices in high voltage discrete power devices. We examine the same charge balance concept in a fast recovery diode and a MOSFET. This is crucial in the extending system performance at compact dimensions. At smaller device and system sizes, the performance trade-off between the ON and OFF states becomes all the more critical. The focus on reducing the switching losses while maintaining system reliability increases. In a conventional planar technology, the technology places a limit on the switching performance owing to the larger die sizes. Using a charge balance structure helps achieve the improved trade-off, while working towards ultimately improving system reliability, size and cost.Chapter 1 introduces the basic power system based on an inductive switching circuit, and the various components that determine its efficiency. Chapter 2 presents a novel Trench Fast Recovery Diode (FRD) structure with injection control is proposed in this dissertation. The proposed structure achieves improved carrier profile without the need for excess lifetime control. This substantially improves the device performance, especially at extreme temperatures (-40oC to 175oC). The device maintains low leakage at high temperatures, and it's Qrr and Irm do not degrade as is the usual case in heavily electron radiated devices. A 1600 diode using this structure has been developed, with a low forward turn-on voltage and good reverse recovery properties. The experimental results show that the structure maintains its performance at high temperatures.In chapter 3, we develop a termination scheme for the previously mentioned diode. A major limitation on the performance of high voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The termination scheme was applied towards a 1350 V fast recovery diode, and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after High Temperature Reverse Bias testing due to mobile ion contamination from packaging mold compound.In chapter 4, we also investigate the device physics behind a superjunction MOSFET structure for improved robustness. The biggest issue with a completely charge balanced MOSFET is decreased robustness in an Unclamped Inductive Switching (UIS) Circuit. The equally charged P and N pillars result in a flat electric field profile, with the peak carrier density closer to the P-N junction at the surface. This results in an almost negligible positive dynamic Rds-on effect in the MOSFET. By changing the charge profile of the P-column, either by increasing it completely or by implementing a graded profile with the heavier P on top, we can change the field profile and shift the carrier density deeper into silicon, increasing the positive dynamic Rds-on effect. Simulation and experimental results are presented to support the theory and understanding.Chapter 5 summarizes all the theories presented and the contributions made by them in the field. It also seeks to highlight future work to be done in these areas.
Show less - Date Issued
- 2016
- Identifier
- CFE0006158, ucf:51148
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006158
- Title
- Uncooled Infrared Detector Featuring Silicon based Nanoscale Thermocouple.
- Creator
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Modarres-Zadeh, Mohammad, Abdolvand, Reza, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Malocha, Donald, Cho, Hyoung Jin, University of Central Florida
- Abstract / Description
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The main focus of this dissertation is to improve the performance of thermoelectric (TE)infrared (IR) detectors. TE IR detectors are part of uncooled detectors that can operate at roomtemperature. These detectors have been around for many years, however, their performance hasbeen lower than their contesting technologies. A novel high-responsivity uncooled thermoelectricinfrared detector is designed, fabricated, and characterized. This detector features a single standalonepolysilicon-based...
Show moreThe main focus of this dissertation is to improve the performance of thermoelectric (TE)infrared (IR) detectors. TE IR detectors are part of uncooled detectors that can operate at roomtemperature. These detectors have been around for many years, however, their performance hasbeen lower than their contesting technologies. A novel high-responsivity uncooled thermoelectricinfrared detector is designed, fabricated, and characterized. This detector features a single standalonepolysilicon-based thermocouple (without a supporting membrane) covered by an umbrellalikeoptical-cavity IR absorber. It is proved that the highest responsivity in the developed detectorscan be achieved with only one thermocouple. Since the sub-micrometer polysilicon TE wires arethe only heat path from the hot junction to the substrate, a superior thermal isolation is achieved.A responsivity of 1800 V/W and a detectivity of 2 ? 10^8 (cm. sqrt(Hz)W^?1) are measured from a20?m x 20?m detector comparable to the performance of detectors used in commercial focalplanar arrays. This performance in a compact and manufacturable design elevates the position ofthermoelectric IR sensors as a candidate for low-power, high performance, and inexpensive focalplanar arrays. The improvement in performance is mostly due to low thermal conductivity of thinpolysilicon wires. A feature is designed and fabricated to characterize the thermal conductivity ofsuch a wire and it is shown for the first time that the thermal conductivity of thin polysilicon filmscan be much lower than that of the bulk. Thermal conductivity of ~110nm LPCVD polysilicondeposited at 620C is measured to be ~3.5W/m.K.
Show less - Date Issued
- 2016
- Identifier
- CFE0006537, ucf:51321
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006537
- Title
- Design Disjunction for Resilient Reconfigurable Hardware.
- Creator
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Alzahrani, Ahmad, DeMara, Ronald, Yuan, Jiann-Shiun, Lin, Mingjie, Wang, Jun, Turgut, Damla, University of Central Florida
- Abstract / Description
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Contemporary reconfigurable hardware devices have the capability to achieve high performance, powerefficiency, and adaptability required to meet a wide range of design goals. With scaling challenges facing current complementary metal oxide semiconductor (CMOS), new concepts and methodologies supportingefficient adaptation to handle reliability issues are becoming increasingly prominent. Reconfigurable hardware and their ability to realize self-organization features are expected to play a key...
Show moreContemporary reconfigurable hardware devices have the capability to achieve high performance, powerefficiency, and adaptability required to meet a wide range of design goals. With scaling challenges facing current complementary metal oxide semiconductor (CMOS), new concepts and methodologies supportingefficient adaptation to handle reliability issues are becoming increasingly prominent. Reconfigurable hardware and their ability to realize self-organization features are expected to play a key role in designingfuture dependable hardware architectures. However, the exponential increase in density and complexity of current commercial SRAM-based field-programmable gate arrays (FPGAs) has escalated the overheadassociated with dynamic runtime design adaptation. Traditionally, static modular redundancy techniques areconsidered to surmount this limitation; however, they can incur substantial overheads in both area andpower requirements. To achieve a better trade-off among performance, area, power, and reliability, thisresearch proposes design-time approaches that enable fine selection of redundancy level based on target reliability goals and autonomous adaptation to runtime demands. To achieve this goal, three studies were conducted:First, a graph and set theoretic approach, named Hypergraph-Cover Diversity (HCD), is introduced as a preemptive design technique to shift the dominant costs of resiliency to design-time. In particular, union-freehypergraphs are exploited to partition the reconfigurable resources pool into highly separable subsets ofresources, each of which can be utilized by the same synthesized application netlist. The diverseimplementations provide reconfiguration-based resilience throughout the system lifetime while avoiding thesignificant overheads associated with runtime placement and routing phases. Evaluation on a Motion-JPEGimage compression core using a Xilinx 7-series-based FPGA hardware platform has demonstrated thepotential of the proposed FT method to achieve 37.5% area saving and up to 66% reduction in powerconsumption compared to the frequently-used TMR scheme while providing superior fault tolerance.Second, Design Disjunction based on non-adaptive group testing is developed to realize a low-overheadfault tolerant system capable of handling self-testing and self-recovery using runtime partial reconfiguration.Reconfiguration is guided by resource grouping procedures which employ non-linear measurements given by the constructive property of f-disjunctness to extend runtime resilience to a large fault space and realize a favorable range of tradeoffs. Disjunct designs are created using the mosaic convergence algorithmdeveloped such that at least one configuration in the library evades any occurrence of up to d resource faults, where d is lower-bounded by f. Experimental results for a set of MCNC and ISCAS benchmarks havedemonstrated f-diagnosability at the individual slice level with average isolation resolution of 96.4% (94.4%) for f=1 (f=2) while incurring an average critical path delay impact of only 1.49% and area cost roughly comparable to conventional 2-MR approaches. Finally, the proposed Design Disjunction method is evaluated as a design-time method to improve timing yield in the presence of large random within-die (WID) process variations for application with a moderately high production capacity.
Show less - Date Issued
- 2015
- Identifier
- CFE0006250, ucf:51086
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006250
- Title
- Enhanced Hardware Security Using Charge-Based Emerging Device Technology.
- Creator
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Bi, Yu, Yuan, Jiann-Shiun, Jin, Yier, DeMara, Ronald, Lin, Mingjie, Chow, Lee, University of Central Florida
- Abstract / Description
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The emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these...
Show moreThe emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these primitives based on the currently prevailing CMOS technology.However, the security provided by these primitives comes at the cost of large overheads mostly in terms of area and power consumption. The development of emerging technologies provides hardware security researchers with opportunities to utilize some of the otherwise unusable properties of emerging technologies in security applications. In this dissertation, we will include the security consideration in the overall performance measurements to fully compare the emerging devices with CMOS technology.The first approach is to leverage two emerging devices (Silicon NanoWire and Graphene SymFET) for hardware security applications. Experimental results indicate that emerging device based solutions can provide high level circuit protection with relatively lower performance overhead compared to conventional CMOS counterpart. The second topic is to construct an energy-efficient DPA-resilient block cipher with ultra low-power Tunnel FET. Current-mode logic is adopted as a circuit-level solution to countermeasure differential power analysis attack, which is mostly used in the cryptographic system. The third investigation targets on potential security vulnerability of foundry insider's attack. Split manufacturing is adopted for the protection on radio-frequency (RF) circuit design.
Show less - Date Issued
- 2016
- Identifier
- CFE0006264, ucf:51041
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006264
- Title
- Autonomous Recovery of Reconfigurable Logic Devices using Priority Escalation of Slack.
- Creator
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Imran, Syednaveed, DeMara, Ronald, Mikhael, Wasfy, Lin, Mingjie, Yuan, Jiann-Shiun, Geiger, Christopher, University of Central Florida
- Abstract / Description
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Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases.To extend these concepts to semiconductor aging and process variation in the deep...
Show moreField Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases.To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Reconfigurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric.FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria.
Show less - Date Issued
- 2013
- Identifier
- CFE0005006, ucf:50005
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0005006
- Title
- On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits.
- Creator
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Cui, Qiang, Liou, Juin, Yuan, Jiann-Shiun, Wu, Xinzhang, Haralambous, Michael, Shen, Zheng, Deppe, Dennis, University of Central Florida
- Abstract / Description
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Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD...
Show moreElectrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS.The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT's snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Post-snapback saturation is caused by temperature-induced mobility degradation due to III-V compound semiconductor materials' poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT's InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancement-mode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ((>) 5.2 A It2) under HBM. Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process.In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR's impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter.Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys.
Show less - Date Issued
- 2013
- Identifier
- CFE0004668, ucf:49848
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004668
