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A NON-ISOLATED HALF BRIDGE BUCK-BASED CONVERTER FOR VRM APPLICATION AND SMALL SIGNAL MODELING OF A NON-CONVENTIONAL TWO PHASE BUCK
Title
A NON-ISOLATED HALF BRIDGE BUCK-BASED CONVERTER FOR VRM APPLICATION AND SMALL SIGNAL MODELING OF A NON-CONVENTIONAL TWO PHASE BUCK.
Creator
Batarseh, Majd, Batarseh, Issa, University of Central Florida
Abstract / Description
The challenges imposed on Voltage Regulator Modules (VRM) become difficult to be achieved with the conventional multiphase buck converter commonly used on PC motherboards. For faster data transfer, a decrease in the output voltage is needed. This decrease causes small duty cycle that is accompanied by critical problems which impairs the efficiency. Therefore, these problems need to be addressed. Transformer-based non-isolated topologies are not new approaches to extend the duty cycle and...
Show moreThe challenges imposed on Voltage Regulator Modules (VRM) become difficult to be achieved with the conventional multiphase buck converter commonly used on PC motherboards. For faster data transfer, a decrease in the output voltage is needed. This decrease causes small duty cycle that is accompanied by critical problems which impairs the efficiency. Therefore, these problems need to be addressed. Transformer-based non-isolated topologies are not new approaches to extend the duty cycle and avoid the associated drawbacks. High leakage, several added components and complicated driving and control schemes are some of the trade-offs to expand the duty cycle. The objective of this work is to present a new dc-dc buck-based topology, which extends the duty cycle with minimum drawbacks by adding two transformers that can be integrated to decrease the size and two switches with zero voltage switching (ZVS). Another issue addressed in this thesis is deriving a small signal model for a two-input two-phase buck converter as an introduction to a new evolving field of multi-input converters.
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Date Issued
2006
Identifier
CFE0001513, ucf:47130
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001513
DIGITAL PULSE WIDTH MODULATOR TECHNIQUES FOR DC - DC CONVERTERS
Title
DIGITAL PULSE WIDTH MODULATOR TECHNIQUES FOR DC - DC CONVERTERS.
Creator
Batarseh, Majd, Batarseh, Issa, University of Central Florida
Abstract / Description
Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC - DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed...
Show moreRecent research activities focused on improving the steady-state as well as the dynamic behavior of DC - DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture,based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit.
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Date Issued
2010
Identifier
CFE0003055, ucf:48314
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003055