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Title: Exploring FPGA Implementation for Binarized Neural Network Inference.
Creator: Yang, Li, Fan, Deliang, Zhang, Wei, Lin, Mingjie, University of Central Florida
Abstract / Description: Deep convolutional neural network has taken an important role in machine learning algorithm. It is widely used in different areas such as computer vision, robotics, and biology. However, the models of deep neural networks become larger and more computation complexity which is a big obstacle for such huge model to implement on embedded systems. Recent works have shown the binarized neural networks (BNN), utilizing binarized (i.e. +1 and -1) convolution kernel and binarized activation function,...
Show moreDeep convolutional neural network has taken an important role in machine learning algorithm. It is widely used in different areas such as computer vision, robotics, and biology. However, the models of deep neural networks become larger and more computation complexity which is a big obstacle for such huge model to implement on embedded systems. Recent works have shown the binarized neural networks (BNN), utilizing binarized (i.e. +1 and -1) convolution kernel and binarized activation function, can significantly reduce the parameter size and computation cost, which makes it hardware-friendly for Field-Programmable Gate Arrays (FPGAs) implementation with efficient energy cost. This thesis proposes to implement a new parallel convolutional binarized neural network (i.e. PC-BNN) on FPGA with accurate inference. The embedded PC-BNN is designed for image classification on CIFAR-10 dataset and explores the hardware architecture and optimization of customized CNN topology.The parallel-convolution binarized neural network has two parallel binarized convolution layers which replaces the original single binarized convolution layer. It achieves around 86% on CIFAR-10 dataset and owns 2.3Mb parameter size. We implement our PC-BNN inference into the Xilinx PYNQ Z1 FPGA board which only has 4.9Mb on-chip Block RAM. Since the ultra-small network parameter, the whole model parameters can be stored on on-chip memory which can greatly reduce energy consumption and computation latency. Meanwhile, we design a new pipeline streaming architecture for PC-BNN hardware inference which can further increase the performance. The experiment results show that our PC-BNN inference on FPGA achieves 930 frames per second and 387.5 FPS/Watt, which are among the best throughput and energy efficiency compared to most recent works.
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Date Issued: 2018
Identifier: CFE0007384, ucf:52067
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007384

Title: Reducing the Overhead of Memory Space, Network Communication and Disk I/O for Analytic Frameworks in Big Data Ecosystem.
Creator: Zhang, Xuhong, Wang, Jun, Fan, Deliang, Lin, Mingjie, Zhang, Shaojie, University of Central Florida
Abstract / Description: To facilitate big data processing, many distributed analytic frameworks and storage systems such as Apache Hadoop, Apache Hama, Apache Spark and Hadoop Distributed File System (HDFS) have been developed. Currently, many researchers are conducting research to either make them more scalable or enabling them to support more analysis applications. In my PhD study, I conducted three main works in this topic, which are minimizing the communication delay in Apache Hama, minimizing the memory space...
Show moreTo facilitate big data processing, many distributed analytic frameworks and storage systems such as Apache Hadoop, Apache Hama, Apache Spark and Hadoop Distributed File System (HDFS) have been developed. Currently, many researchers are conducting research to either make them more scalable or enabling them to support more analysis applications. In my PhD study, I conducted three main works in this topic, which are minimizing the communication delay in Apache Hama, minimizing the memory space and computational overhead in HDFS and minimizing the disk I/O overhead for approximation applications in Hadoop ecosystem. Specifically, In Apache Hama, communication delay makes up a large percentage of the overall graph processing time. While most recent research has focused on reducing the number of network messages, we add a runtime communication and computation scheduler to overlap them as much as possible. As a result, communication delay can be mitigated. In HDFS, the block location table and its corresponding maintenance could occupy more than half of the memory space and 30% of processing capacity in master node, which severely limit the scalability and performance of master node. We propose Deister that uses deterministic mathematical calculations to eliminate the huge table for storing the block locations and its corresponding maintenance. My third work proposes to enable both efficient and accurate approximations on arbitrary sub-datasets of a large dataset. Existing offline sampling based approximation systems are not adaptive to dynamic query workloads and online sampling based approximation systems suffer from low I/O efficiency and poor estimation accuracy. Therefore, we develop a distribution aware method called Sapprox. Our idea is to collect the occurrences of a sub-dataset at each logical partition of a dataset (storage distribution) in the distributed system at a very small cost, and make good use of such information to facilitate online sampling.
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Date Issued: 2017
Identifier: CFE0007299, ucf:52149
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007299

Title: Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation.
Creator: Mendoza Macias, Raul, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Fan, Deliang, University of Central Florida
Abstract / Description: Vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In...
Show moreVertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In addition, electrical parameters such as threshold voltage and charge balance are also examined. Increasing the superjunction doping in the drift region of VDMOS reduces the on-resistance by 26%, while maintaining the same breakdown voltage and threshold voltage compared to that of the conventional VDMOS power transistor with similar device design without using a superjunction.
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Date Issued: 2016
Identifier: CFE0006354, ucf:51525
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006354

Title: Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories.
Creator: Salehi Mobarakeh, Soheil, DeMara, Ronald, Fan, Deliang, Turgut, Damla, University of Central Florida
Abstract / Description: The continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation....
Show moreThe continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time.
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Date Issued: 2016
Identifier: CFE0006493, ucf:51400
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006493

Title: Three-Dimensional Simulation Study of Low Voltage ((<)100V) Superjunction Lateral DMOS power transistors.
Creator: Garcia, Jhonatan, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Fan, Deliang, University of Central Florida
Abstract / Description: A new revolutionary concept was presented two decades ago, known as (")semiconductor Superjunction (SJ) theory(") to enhance the trade-off relationship between speci?c on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was ?rst applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures,...
Show moreA new revolutionary concept was presented two decades ago, known as (")semiconductor Superjunction (SJ) theory(") to enhance the trade-off relationship between speci?c on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was ?rst applied and commercialized to vertical structures, but it hasn't been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures, principles and design techniques for discrete power MOSFETs. It also presents a simulation study of the application of these SJ concepts in the design of a Low Voltage SJ LDMOS transistor, using TCAD software. To make the device commercially feasible, this device design targets aggressive goals such as an off-state Breakdown Voltage of 60V with Rspof 20 miliohms per milimiter square. This study includes the analysis of the ?ow process for the fabrication of this transistor, using semiconductor technologies, and the simulation results, including Breakdown Voltage, on-state resistance, electric ?eld distribution among others simulation analysis.
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Date Issued: 2016
Identifier: CFE0006306, ucf:51600
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006306

Title: Bridging the Gap between Application and Solid-State-Drives.
Creator: Zhou, Jian, Wang, Jun, Lin, Mingjie, Fan, Deliang, Ewetz, Rickard, Qi, GuoJun, University of Central Florida
Abstract / Description: Data storage is one of the important and often critical parts of the computing systemin terms of performance, cost, reliability, and energy.Numerous new memory technologies,such as NAND flash, phase change memory (PCM), magnetic RAM (STT-RAM) and Memristor,have emerged recently.Many of them have already entered the production system.Traditional storage optimization and caching algorithms are far from optimalbecause storage I/Os do not show simple locality.To provide optimal storage we need...
Show moreData storage is one of the important and often critical parts of the computing systemin terms of performance, cost, reliability, and energy.Numerous new memory technologies,such as NAND flash, phase change memory (PCM), magnetic RAM (STT-RAM) and Memristor,have emerged recently.Many of them have already entered the production system.Traditional storage optimization and caching algorithms are far from optimalbecause storage I/Os do not show simple locality.To provide optimal storage we need accurate predictions of I/O behavior.However, the workloads are increasingly dynamic and diverse,making the long and short time I/O prediction challenge.Because of the evolution of the storage technologiesand the increasing diversity of workloads,the storage software is becoming more and more complex.For example, Flash Translation Layer (FTL) is added for NAND-flash based Solid State Disks (NAND-SSDs).However, it introduces overhead such as address translation delay and garbage collection costs.There are many recent studies aim to address the overhead.Unfortunately, there is no one-size-fits-all solution due to the variety of workloads.Despite rapidly evolving in storage technologies,the increasing heterogeneity and diversity in machines and workloadscoupled with the continued data explosionexacerbate the gap between computing and storage speeds.In this dissertation, we improve the data storage performance from both top-down and bottom-up approach.First, we will investigate exposing the storage level parallelismso that applications can avoid I/O contentions and workloads skewwhen scheduling the jobs.Second, we will study how architecture aware task scheduling can improve the performance of the application when PCM based NVRAM are equipped.Third, we will develop an I/O correlation aware flash translation layer for NAND-flash based Solid State Disks.Fourth, we will build a DRAM-based correlation aware FTL emulator and study the performance in various filesystems.
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Date Issued: 2018
Identifier: CFE0007273, ucf:52188
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007273

Title: Heterogeneous Reconfigurable Fabrics for In-circuit Training and Evaluation of Neuromorphic Architectures.
Creator: Mohammadizand, Ramtin, DeMara, Ronald, Lin, Mingjie, Sundaram, Kalpathy, Fan, Deliang, Wu, Annie, University of Central Florida
Abstract / Description: A heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over...
Show moreA heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over fabrics having LUTs constructed with either individual technology alone. Herein, a hierarchical top-down design approach is used to develop the HSC(&)#173; FPGA starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication paradigms. This facilitates a novel architectural approach to reduce leakage energy, minimize communication occurrence and energy cost by eliminating unnecessary data transfer, and support auto-tuning for resilience. Furthermore, HSC-FPGA enables new advantages of technology co-design which trades off alternative mappings between emerging devices and transistors at runtime by allowing dynamic remapping to adaptively leverage the intrinsic computing features of each device technology. HSC-FPGA offers a platform for fine-grained Logic-In-Memory architectures and runtime adaptive hardware.An orthogonal dimension of fabric heterogeneity is also non-determinism enabled by either low(&)#173; voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Herein, consider the probabilistic spin logic p-bit device as a fabric element comprising a crossbar(&)#173; structured weighted array. The programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array's weighted connections. Thus, the programmable weighted array forms a CLB-scale macro co-processing element with bitstream programmability. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n(&)#215; m1(&)#215;m2(&)#215;...(&)#215;mi weighted array as a configurable hardware circuit with an n-input layer followed by i?1 hidden layers. As neuromorphic architectures using post-CMOS devices increase in capability and network size, the utility and benefits of reconfigurable fabrics of neuromorphic modules can be anticipated to continue to accelerate.
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Date Issued: 2019
Identifier: CFE0007502, ucf:52643
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007502

Title: Automated Synthesis of Unconventional Computing Systems.
Creator: Hassen, Amad Ul, Jha, Sumit Kumar, Sundaram, Kalpathy, Fan, Deliang, Ewetz, Rickard, Rahman, Talat, University of Central Florida
Abstract / Description: Despite decades of advancements, modern computing systems which are based on the von Neumann architecture still carry its shortcomings. Moore's law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes. On the other hand, modern computational requirements, driven by machine learning, pattern recognition, artificial intelligence, data mining, and IoT, are growing...
Show moreDespite decades of advancements, modern computing systems which are based on the von Neumann architecture still carry its shortcomings. Moore's law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes. On the other hand, modern computational requirements, driven by machine learning, pattern recognition, artificial intelligence, data mining, and IoT, are growing at the fastest pace ever. By their inherent nature, these applications are particularly affected by communication-bottlenecks, because processing them requires a large number of simple operations involving data retrieval and storage. The need to address the problems associated with conventional computing systems at the fundamental level has given rise to several unconventional computing paradigms. In this dissertation, we have made advancements for automated syntheses of two types of unconventional computing paradigms: in-memory computing and stochastic computing. In-memory computing circumvents the problem of limited communication bandwidth by unifying processing and storage at the same physical locations. The advent of nanoelectronic devices in the last decade has made in-memory computing an energy-, area-, and cost-effective alternative to conventional computing. We have used Binary Decision Diagrams (BDDs) for in-memory computing on memristor crossbars. Specifically, we have used Free-BDDs, a special class of binary decision diagrams, for synthesizing crossbars for flow-based in-memory computing. Stochastic computing is a re-emerging discipline with several times smaller area/power requirements as compared to conventional computing systems. It is especially suited for fault-tolerant applications like image processing, artificial intelligence, pattern recognition, etc. We have proposed a decision procedures-based iterative algorithm to synthesize Linear Finite State Machines (LFSM) for stochastically computing non-linear functions such as polynomials, exponentials, and hyperbolic functions.
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Date Issued: 2019
Identifier: CFE0007648, ucf:52462
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007648

Title: Design, Simulation and Characterization of Novel Electrostatic Discharge Protection Devices and Circuits in Advanced Silicon Technologies.
Creator: Liang, Wei, Sundaram, Kalpathy, Fan, Deliang, Jin, Yier, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be...
Show moreElectrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be destroyed easily, so ESD protection solutions are essential to semiconductor industry.ESD protection design consists of on-chip and off-chip ESD protection design, and the research works in this dissertation are all conducted in on-chip level, which incorporate the ESD protection devices and circuits into the microchip, to provide with basic ESD protection from manufacturing to customer use. The basic idea of ESD protection design is to provide a path with low impedance which directs most of the ESD current to flow through itself instead of the core circuit, and the ESD protection path must be robust enough to make sure that it does not fail before the core circuit. In this way, proper design on protection devices and circuits should be considered carefully. To assist the understanding and design of ESD protection, the ESD event in real world has been classified into a few ESD model including Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM), etc. Some mainstream testing method and industry standard are also introduced, including Transmission Line Pulse (TLP), and IEC 61000-4-2. ESD protection devices including diode, Gate-Grounded N-type MOSFET (GGNMOS), Silicon Controlled Rectifier (SCR) are basic elements for ESD protection design. In this dissertation, the device characteristics in ESD event and their applications are introduced. From the perspective of the whole chip ESD protection design, the concept of circuit level ESD protection and the ESD clamps are also briefly introduced. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation is widely used in ESD protection design. In this dissertation, TCAD and SPICE simulation are carried out for a few times for both of pre-tapeout evaluation on characteristics of the proposed device and circuit and post-tapeout analysis on structure operating mechanism.Automotive electronics has been a popular subject in semiconductor industry, and due to the special requirement of the automotive applications like the capacitive pins, the ESD protection device used in such applications need to be specially designed. In this dissertation, a few SCRs without snapback are discussed in detail. To avoid core circuit damages caused the displacement current induced by the large snapback in conventional SCR, an eliminated/minimized snapback is preferred in a selection of the protection device. Two novel SCRs are proposed for High Voltage (HV), Medium Voltage (MV), and Low Voltage (LV) automotive ESD protection.The typical operating temperature for ICs is up to 125 (&)#186;C, however in automotive applications, the operating temperature may extend up to 850 (&)#186;C. In this way, the characteristics of the ESD protection device under the elevated temperatures will be an essential part to investigate for automotive ESD protection design. In this dissertation, the high temperature characteristics of ESD protection devices including diode and a few SCRs is measured and discussed in detail. TCAD simulation are also conducted to explain the underlying physical mechanism. This work provides with a useful insight and information to ESD protection design in high temperature applications.Besides the high temperature environment, ESD protection are also highly needed for electronics working in other extreme environment like the space. Space is an environment that contains kinds of radiation source and at the same time can generate abundant ESD. The ESD adhering to the space systems could be a potential threat to the space electronics. At the same time, the characteristics of the ESD protection part especially the basic protection device used in the space electronics could be influenced after the irradiation in the space. Therefore, the investigation of the radiation effects on ESD protection devices are necessary. In this dissertation, the total ionizing dose (TID) effects on ESD protection devices are investigated. The devices are irradiated with 1.5 MeV He+ and characterized with TLP tester. The pre- and post-irradiation characteristics are compared and the variation on key ESD parameters are analyzed and discussed. This work offers a useful insight on ESD devices' operation under TID and help with the device designing on ESD protection devices for space electronics.Single ESD protection devices are essential part constructing the ESD protection network, however the optimization on ESD clamp circuit design is also important on building an efficient whole chip ESD protection network. In this dissertation, the design and simulation of a novel voltage triggered ESD detection circuit are introduced. The voltage triggered ESD detection circuit is proposed in a 0.18 um CMOS technology. Comparing with the conventional RC based detection circuit, the proposed circuit realizes a higher triggering efficiency with a much smaller footprint, and is immune to false triggering under fast power-up events. The proposed circuit has a better sensitivity to ESD event and is more reliable in ESD protection applications.The leakage current has been a concern with the scaling down of the thickness of the gate oxide. Therefore, a proper design of the ESD clamp for power rail ESD protection need to be specially considered. In this dissertation, a design of a novel ESD clamp with low leakage current is analyzed. The proposed clamp realized a pretty low leakage current up to 12 nA, and has a smaller footprint than conventional design. It also has a long hold-on time under ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the operation of the proposed ESD clamp.
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Date Issued: 2017
Identifier: CFE0007126, ucf:52298
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007126

Title: Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies.
Creator: Dong, Aihua, Sundaram, Kalpathy, Fan, Deliang, Gong, Xun, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to...
Show moreElectrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to FinFET technology requires more robust ESD protection however the large parasitic capacitance of ESD protection cell is problematic in high-speed interface design. To reduce the parasitic capacitance, a dual diode silicon controlled rectifier (DD-SCR) is presented in this dissertation. This design can exhibit good trade-offs between ESD robustness and parasitic capacitance characteristics. Besides, different bounding materials lead to performance variations in DD-SCRs are compared. Radio frequency (RF) technology is also demanded low capacitance ESD protection. To address this concern, a ?-network is presented, providing robust ESD protection for 10-60 GHz RF circuit. Like a low pass ? filter, the network can reflect high frequency RF signals and transmit low frequency ESD pulses. Given proper inductor value, networks can work as robust ESD solutions at a certain Giga Hertz frequency range, making this design suitable for broad band protection in RF input/outputs (I/Os). To increase the holding voltage and reduce snapback, a resistor assist triggering heterogeneous stacking structure is presented in this dissertation, which can increase the holding voltage and also keep the trigger voltage nearly as same as a single SCR device.
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Date Issued: 2018
Identifier: CFE0007172, ucf:52251
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007172

Title: Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions.
Creator: Li, Hang, Sundaram, Kalpathy, Batarseh, Issa, Fan, Deliang, Gong, Xun, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A...
Show moreElectrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A compact model is developed to predict thermal failure with circuit simulators. Instead of considering the detailed failure mechanisms, a failure temperature is introduced to indicate device failure. The developed model is implemented by a multiple-stage thermal network.P-N junction is the fundamental structure for ESD protection devices. An enhanced diode model is proposed and is used to simulate the device behaviors for ESD events. The model includes all physical effects for ESD conditions, which are voltage overshoot, self-heating effect, velocity saturation and thermal failure. The proposed model not only can fit the I-V and transient characteristics, but also can predict failure for different pulses.Safe Operating Area (SOA) is an important factor to evaluate the LDMOS performance. The transient SOA boundary is considered as power-defined. By placing the failure monitor under certain conditions, the developed modeling methodology can predict the boundary of transient SOA for any short pulse stress conditions. No matter failure happens before or after snapback phenomenon.Weibull distribution is popular to evaluate the dielectric lifetime for CVS. By using the transformative version of power law, the pulsing stresses are converted into CVS, and TDDB under ESD conditions for SiN MIMCAPs is analyzed. The thickness dependency and area independency of capacitor breakdown voltage is observed, which can be explained by the constant ?E model instead of conventional percolation model.
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Date Issued: 2019
Identifier: CFE0007670, ucf:52512
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007670

Title: Normally-Off Computing Design Methodology Using Spintronics: from Devices to Architectures.
Creator: Roohi, Arman, DeMara, Ronald, Abdolvand, Reza, Wang, Jun, Fan, Deliang, Del Barco, Enrique, University of Central Florida
Abstract / Description: Energy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle...
Show moreEnergy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle-variable computing approach leveraging the non-volatility inherent in post-CMOS switching devices. The foundations of EIC will be advanced from the ground up by extending Spin Hall Effect Magnetic Tunnel Junction (SHE-MTJ) device models to realize SHE-MTJ-based Majority Gate (MG) and Polymorphic Gate (PG) logic approaches and libraries, that leverage intrinsic-non-volatility to realize middleware-coherent, intermittent computation without checkpointing, micro-tasking, or software bloat and energy overheads vital to IoT. Device-level EIC research concentrates on encapsulating SHE-MTJ behavior with a compact model to leverage the non-volatility of the device for intrinsic provision of intermittent computation and lifetime energy reduction. Based on this model, the circuit-level EIC contributions will entail the design, simulation, and analysis of PG-based spintronic logic which is adaptable at the gate-level to support variable duty cycle execution that is robust to brief and extended supply outages or unscheduled dropouts, and development of spin-based research synthesis and optimization routines compatible with existing commercial toolchains. These tools will be employed to design a hybrid post-CMOS processing unit utilizing pipelining and power-gating through state-holding properties within the datapath itself, thus eliminating checkpointing and data transfer operations.
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Date Issued: 2019
Identifier: CFE0007526, ucf:52619
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007526

Title: Towards High-Efficiency Data Management In the Next-Generation Persistent Memory System.
Creator: Chen, Xunchao, Wang, Jun, Fan, Deliang, Lin, Mingjie, Ewetz, Rickard, Zhang, Shaojie, University of Central Florida
Abstract / Description: For the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM). However, in order to mitigate the write disturbance in an MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. Furthermore, as the result of MTJ feature size scaling, the soft...
Show moreFor the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM). However, in order to mitigate the write disturbance in an MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. Furthermore, as the result of MTJ feature size scaling, the soft bit can be expected to become disturbed by the read sensing current, thus requiring an immediate restore operation to ensure the data reliability. In this paper, we design and analyze a novel Adaptive Restore Scheme for Write Disturbance (ARS-WD) and Read Disturbance (ARS-RD), respectively. ARS-WD alleviates restoration overhead by intentionally overwriting soft bit lines which are less likely to be read. ARS-RD, on the other hand, aggregates the potential writes and restore the soft bit line at the time of its eviction from higher level cache. Both of these two schemes are based on a lightweight forecasting approach for the future read behavior of the cache block. Our experimental results show substantial reduction in soft bit line restore operations. Moreover, ARS promotes advantages of MLC to provide a preferable L2 design alternative in terms of energy, area and latency product compared to SLC STT-RAM alternatives. Whereas the popular Cell Split Mapping (CSM) for MLC STT-RAM leverages the inter-block nonuniform access frequency, the intra-block data access features remain untapped in the MLC design. Aiming to minimize the energy-hungry write request to Hard-Bit Line (HBL) and maximize the dynamic range in the advantageous Soft-Bit Line (SBL), an hybrid mapping strategy for MLC STT-RAM cache (Double-S) is advocated in the paper. Double-S couples the contemporary Cell-Split-Mapping with the novel Word-Split-Mapping (WSM). Sparse cache block detector and read depth based data allocation/ migration policy are proposed to release the full potential of Double-S.
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Date Issued: 2017
Identifier: CFE0006865, ucf:51751
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006865

ESD (3)	+ -
Approximation (1)	+ -
Approximative Computing (1)	+ -
Communication (1)	+ -
Data Correlation (1)	+ -

Deep Belief Network (DBN) (1)	+ -
Diode (1)	+ -
Energy Efficient (1)	+ -
FBDD (1)	+ -
FPGA (1)	+ -
Flash Translation Layer (1)	+ -
GGNMOS (1)	+ -
HDFS (1)	+ -
Hadoop (1)	+ -
Hybrid-Technology FPGA (1)	+ -
I/O (1)	+ -
LDMOS (1)	+ -
Low Power (1)	+ -
Low-power computation (1)	+ -
Magnetic Tunnel Junction (MTJ) (1)	+ -
Power Clamp (1)	+ -
Power MOSFET (1)	+ -
Probabilistic Spin Logic Devices (1)	+ -
Process Variation (1)	+ -
ROBDD (1)	+ -
Reconfigurable Fabric (1)	+ -
Reliability (1)	+ -
Restricted Boltzmann Machine (RBM) (1)	+ -
SCR (1)	+ -
STT-MRAM (1)	+ -

Fan, Deliang (13)	+ -
University of Central Florida (13)	+ -
Sundaram, Kalpathy (7)	+ -
Lin, Mingjie (5)	+ -
Wang, Jun (4)	+ -

DeMara, Ronald (3)	+ -
Ewetz, Rickard (3)	+ -
Salcedo, Javier (3)	+ -
Gong, Xun (2)	+ -
Wei, Lei (2)	+ -
Yuan, Jiann-Shiun (2)	+ -
Zhang, Shaojie (2)	+ -
Abdolvand, Reza (1)	+ -
Batarseh, Issa (1)	+ -
Chen, Xunchao (1)	+ -
Del Barco, Enrique (1)	+ -
Dong, Aihua (1)	+ -
Garcia, Jhonatan (1)	+ -
Hassen, Amad Ul (1)	+ -
Jha, Sumit Kumar (1)	+ -
Jin, Yier (1)	+ -
Li, Hang (1)	+ -
Liang, Wei (1)	+ -
Mendoza Macias, Raul (1)	+ -
Mohammadizand, Ramtin (1)	+ -
Qi, GuoJun (1)	+ -
Rahman, Talat (1)	+ -
Roohi, Arman (1)	+ -
Salehi Mobarakeh, Soheil (1)	+ -
Turgut, Damla (1)	+ -

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