Current Search: Jadaa, Rami (x)
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Title
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The Performance and Power Impact of Using Multiple DRAM Address Mapping Schemes in Multicore Processors.
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Creator
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Jadaa, Rami, Heinrich, Mark, DeMara, Ronald, Yuan, Jiann-Shiun, University of Central Florida
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Abstract / Description
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Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic...
Show moreLowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications' performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing un-accessed devices to be put into power-down mode, hence saving power to meet a certain power budget.
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Date Issued
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2011
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Identifier
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CFE0004121, ucf:49118
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Format
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Document (PDF)
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PURL
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http://purl.flvc.org/ucf/fd/CFE0004121
