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Title: Developing new power management and High-Reliability Schemes in Data-Intensive Environment.
Creator: Wang, Ruijun, Wang, Jun, Jin, Yier, DeMara, Ronald, Zhang, Shaojie, Ni, Liqiang, University of Central Florida
Abstract / Description: With the increasing popularity of data-intensive applications as well as the large-scale computingand storage systems, current data centers and supercomputers are often dealing with extremelylarge data-sets. To store and process this huge amount of data reliably and energy-efficiently,three major challenges should be taken into consideration for the system designers. Firstly, power conservation(-)Multicore processors or CMPs have become a mainstream in the current processormarket because of...
Show moreWith the increasing popularity of data-intensive applications as well as the large-scale computingand storage systems, current data centers and supercomputers are often dealing with extremelylarge data-sets. To store and process this huge amount of data reliably and energy-efficiently,three major challenges should be taken into consideration for the system designers. Firstly, power conservation(-)Multicore processors or CMPs have become a mainstream in the current processormarket because of the tremendous improvement in transistor density and the advancement in semiconductor technology. However, the increasing number of transistors on a single die or chip reveals a super-linear growth in power consumption [4]. Thus, how to balance system performance andpower-saving is a critical issue which needs to be solved effectively. Secondly, system reliability(-)Reliability is a critical metric in the design and development of replication-based big data storagesystems such as Hadoop File System (HDFS). In the system with thousands machines and storagedevices, even in-frequent failures become likely. In Google File System, the annual disk failurerate is 2:88%,which means you were expected to see 8,760 disk failures in a year. Unfortunately,given an increasing number of node failures, how often a cluster starts losing data when beingscaled out is not well investigated. Thirdly, energy efficiency(-)The fast processing speeds of the current generation of supercomputers provide a great convenience to scientists dealing with extremely large data sets. The next generation of (")exascale(") supercomputers could provide accuratesimulation results for the automobile industry, aerospace industry, and even nuclear fusion reactors for the very first time. However, the energy cost of super-computing is extremely high, with a total electricity bill of 9 million dollars per year. Thus, conserving energy and increasing the energy efficiency of supercomputers has become critical in recent years.This dissertation proposes new solutions to address the above three key challenges for currentlarge-scale storage and computing systems. Firstly, we propose a novel power management scheme called MAR (model-free, adaptive, rule-based) in multiprocessor systems to minimize the CPU power consumption subject to performance constraints. By introducing new I/O wait status, MAR is able to accurately describe the relationship between core frequencies, performance and power consumption. Moreover, we adopt a model-free control method to filter out the I/O wait status from the traditional CPU busy/idle model in order to achieve fast responsiveness to burst situations and take full advantage of power saving. Our extensive experiments on a physical testbed demonstrate that, for SPEC benchmarks and data-intensive (TPC-C) benchmarks, an MAR prototype system achieves 95.8-97.8% accuracy of the ideal power saving strategy calculated offline. Compared with baseline solutions, MAR is able to save 12.3-16.1% more power while maintain a comparable performance loss of about 0.78-1.08%. In addition, more simulation results indicate that our design achieved 3.35-14.2% more power saving efficiency and 4.2-10.7% less performance loss under various CMP configurations as compared with various baseline approaches such as LAST, Relax,PID and MPC.Secondly, we create a new reliability model by incorporating the probability of replica loss toinvestigate the system reliability of multi-way declustering data layouts and analyze their potential parallel recovery possibilities. Our comprehensive simulation results on Matlab and SHARPE show that the shifted declustering data layout outperforms the random declustering layout in a multi-way replication scale-out architecture, in terms of data loss probability and system reliability by upto 63% and 85% respectively. Our study on both 5-year and 10-year system reliability equipped with various recovery bandwidth settings shows that, the shifted declustering layout surpasses the two baseline approaches in both cases by consuming up to 79 % and 87% less recovery bandwidth for copyset, as well as 4.8% and 10.2% less recovery bandwidth for random layout.Thirdly, we develop a power-aware job scheduler by applying a rule based control method and takinginto account real world power and speedup profiles to improve power efficiency while adheringto predetermined power constraints. The intensive simulation results shown that our proposed method is able to achieve the maximum utilization of computing resources as compared to baselinescheduling algorithms while keeping the energy cost under the threshold. Moreover, by introducinga Power Performance Factor (PPF) based on the real world power and speedup profiles, we areable to increase the power efficiency by up to 75%.
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Date Issued: 2016
Identifier: CFE0006704, ucf:51907
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006704

Title: Stochastic-Based Computing with Emerging Spin-Based Device Technologies.
Creator: Bai, Yu, Lin, Mingjie, DeMara, Ronald, Wang, Jun, Jin, Yier, Dong, Yajie, University of Central Florida
Abstract / Description: In this dissertation, analog and emerging device physics is explored to provide a technology plat- form to design new bio-inspired system and novel architecture. With CMOS approaching the nano-scaling, their physics limits in feature size. Therefore, their physical device characteristics will pose severe challenges to constructing robust digital circuitry. Unlike transistor defects due to fabrication imperfection, quantum-related switching uncertainties will seriously increase their sus-...
Show moreIn this dissertation, analog and emerging device physics is explored to provide a technology plat- form to design new bio-inspired system and novel architecture. With CMOS approaching the nano-scaling, their physics limits in feature size. Therefore, their physical device characteristics will pose severe challenges to constructing robust digital circuitry. Unlike transistor defects due to fabrication imperfection, quantum-related switching uncertainties will seriously increase their sus- ceptibility to noise, thus rendering the traditional thinking and logic design techniques inadequate. Therefore, the trend of current research objectives is to create a non-Boolean high-level compu- tational model and map it directly to the unique operational properties of new, power efficient, nanoscale devices.The focus of this research is based on two-fold: 1) Investigation of the physical hysteresis switching behaviors of domain wall device. We analyze phenomenon of domain wall device and identify hys- teresis behavior with current range. We proposed the Domain-Wall-Motion-based (DWM) NCL circuit that achieves approximately 30x and 8x improvements in energy efficiency and chip layout area, respectively, over its equivalent CMOS design, while maintaining similar delay performance for a one bit full adder. 2) Investigation of the physical stochastic switching behaviors of Mag- netic Tunnel Junction (MTJ) device. With analyzing of stochastic switching behaviors of MTJ, we proposed an innovative stochastic-based architecture for implementing artificial neural network (S-ANN) with both magnetic tunneling junction (MTJ) and domain wall motion (DWM) devices, which enables efficient computing at an ultra-low voltage. For a well-known pattern recognition task, our mixed-model HSPICE simulation results have shown that a 34-neuron S-ANN imple- mentation, when compared with its deterministic-based ANN counterparts implemented with dig- ital and analog CMOS circuits, achieves more than 1.5 ? 2 orders of magnitude lower energy consumption and 2 ? 2.5 orders of magnitude less hidden layer chip area.
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Date Issued: 2016
Identifier: CFE0006680, ucf:51921
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006680

Title: DESIGN OF HIGH EFFICIENCY BRUSHLESS PERMANENT MAGNET MACHINES AND DRIVER SYSTEM.
Creator: He, Chengyuan, Wei, Lei, Sundaram, Kalpathy, Zhou, Qun, Jin, Yier, Zou, Shengli, University of Central Florida
Abstract / Description: The dissertation is concerned with the design of high-efficiency permanent magnet synchronous machinery and the control system. The dissertation first talks about the basic concept of the permanent magnet synchronous motor (PMSM) design and the mathematics design model of the advanced design method. The advantage of the design method is that it can increase the high load capacity at no cost of increasing the total machine size. After that, the control method of the PMSM and Permanent magnet...
Show moreThe dissertation is concerned with the design of high-efficiency permanent magnet synchronous machinery and the control system. The dissertation first talks about the basic concept of the permanent magnet synchronous motor (PMSM) design and the mathematics design model of the advanced design method. The advantage of the design method is that it can increase the high load capacity at no cost of increasing the total machine size. After that, the control method of the PMSM and Permanent magnet synchronous generator (PMSG) is introduced. The design, simulation, and test of a permanent magnet brushless DC (BLDC) motor for electric impact wrench and new mechanical structure are first presented based on the design method. Finite element analysis based on the Maxwell 2D is built to optimize the design and the control board is designed using Altium Designer. Both the motor and control board have been fabricated and tested to verify the design. The electrical and mechanical design are combined, and it provides an analytical IPMBLDC design method and an innovative and reasonable mechanical dynamical calculation method for the impact wrench system, which can be used in whole system design of other functional electric tools. A 2kw high-efficiency alternator system and its control board system are also designed, analyzed and fabricated applying to the truck auxiliary power unit (APU). The alternator system has two stages. The first stage is that the alternator three-phase outputs are connected to the three-phase active rectifier to get 48V DC. An advanced Sliding Mode Observer (SMO) is used to get an alternator position. The buck is used for the second stage to get 14V DC output. The whole system efficiency is much higher than the traditional system using induction motor.
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Date Issued: 2018
Identifier: CFE0007334, ucf:52135
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007334

Title: Design, Simulation and Characterization of Novel Electrostatic Discharge Protection Devices and Circuits in Advanced Silicon Technologies.
Creator: Liang, Wei, Sundaram, Kalpathy, Fan, Deliang, Jin, Yier, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be...
Show moreElectrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be destroyed easily, so ESD protection solutions are essential to semiconductor industry.ESD protection design consists of on-chip and off-chip ESD protection design, and the research works in this dissertation are all conducted in on-chip level, which incorporate the ESD protection devices and circuits into the microchip, to provide with basic ESD protection from manufacturing to customer use. The basic idea of ESD protection design is to provide a path with low impedance which directs most of the ESD current to flow through itself instead of the core circuit, and the ESD protection path must be robust enough to make sure that it does not fail before the core circuit. In this way, proper design on protection devices and circuits should be considered carefully. To assist the understanding and design of ESD protection, the ESD event in real world has been classified into a few ESD model including Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM), etc. Some mainstream testing method and industry standard are also introduced, including Transmission Line Pulse (TLP), and IEC 61000-4-2. ESD protection devices including diode, Gate-Grounded N-type MOSFET (GGNMOS), Silicon Controlled Rectifier (SCR) are basic elements for ESD protection design. In this dissertation, the device characteristics in ESD event and their applications are introduced. From the perspective of the whole chip ESD protection design, the concept of circuit level ESD protection and the ESD clamps are also briefly introduced. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation is widely used in ESD protection design. In this dissertation, TCAD and SPICE simulation are carried out for a few times for both of pre-tapeout evaluation on characteristics of the proposed device and circuit and post-tapeout analysis on structure operating mechanism.Automotive electronics has been a popular subject in semiconductor industry, and due to the special requirement of the automotive applications like the capacitive pins, the ESD protection device used in such applications need to be specially designed. In this dissertation, a few SCRs without snapback are discussed in detail. To avoid core circuit damages caused the displacement current induced by the large snapback in conventional SCR, an eliminated/minimized snapback is preferred in a selection of the protection device. Two novel SCRs are proposed for High Voltage (HV), Medium Voltage (MV), and Low Voltage (LV) automotive ESD protection.The typical operating temperature for ICs is up to 125 (&)#186;C, however in automotive applications, the operating temperature may extend up to 850 (&)#186;C. In this way, the characteristics of the ESD protection device under the elevated temperatures will be an essential part to investigate for automotive ESD protection design. In this dissertation, the high temperature characteristics of ESD protection devices including diode and a few SCRs is measured and discussed in detail. TCAD simulation are also conducted to explain the underlying physical mechanism. This work provides with a useful insight and information to ESD protection design in high temperature applications.Besides the high temperature environment, ESD protection are also highly needed for electronics working in other extreme environment like the space. Space is an environment that contains kinds of radiation source and at the same time can generate abundant ESD. The ESD adhering to the space systems could be a potential threat to the space electronics. At the same time, the characteristics of the ESD protection part especially the basic protection device used in the space electronics could be influenced after the irradiation in the space. Therefore, the investigation of the radiation effects on ESD protection devices are necessary. In this dissertation, the total ionizing dose (TID) effects on ESD protection devices are investigated. The devices are irradiated with 1.5 MeV He+ and characterized with TLP tester. The pre- and post-irradiation characteristics are compared and the variation on key ESD parameters are analyzed and discussed. This work offers a useful insight on ESD devices' operation under TID and help with the device designing on ESD protection devices for space electronics.Single ESD protection devices are essential part constructing the ESD protection network, however the optimization on ESD clamp circuit design is also important on building an efficient whole chip ESD protection network. In this dissertation, the design and simulation of a novel voltage triggered ESD detection circuit are introduced. The voltage triggered ESD detection circuit is proposed in a 0.18 um CMOS technology. Comparing with the conventional RC based detection circuit, the proposed circuit realizes a higher triggering efficiency with a much smaller footprint, and is immune to false triggering under fast power-up events. The proposed circuit has a better sensitivity to ESD event and is more reliable in ESD protection applications.The leakage current has been a concern with the scaling down of the thickness of the gate oxide. Therefore, a proper design of the ESD clamp for power rail ESD protection need to be specially considered. In this dissertation, a design of a novel ESD clamp with low leakage current is analyzed. The proposed clamp realized a pretty low leakage current up to 12 nA, and has a smaller footprint than conventional design. It also has a long hold-on time under ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the operation of the proposed ESD clamp.
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Date Issued: 2017
Identifier: CFE0007126, ucf:52298
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007126

Title: Security of Autonomous Systems under Physical Attacks: With application to Self-Driving Cars.
Creator: Dutta, Raj, Jin, Yier, Sundaram, Kalpathy, DeMara, Ronald, Zhang, Shaojie, Zhang, Teng, University of Central Florida
Abstract / Description: The drive to achieve trustworthy autonomous cyber-physical systems (CPS), which can attain goals independently in the presence of significant uncertainties and for long periods of time without any human intervention, has always been enticing. Significant progress has been made in the avenues of both software and hardware for fulfilling these objectives. However, technological challenges still exist and particularly in terms of decision making under uncertainty. In an autonomous system,...
Show moreThe drive to achieve trustworthy autonomous cyber-physical systems (CPS), which can attain goals independently in the presence of significant uncertainties and for long periods of time without any human intervention, has always been enticing. Significant progress has been made in the avenues of both software and hardware for fulfilling these objectives. However, technological challenges still exist and particularly in terms of decision making under uncertainty. In an autonomous system, uncertainties can arise from the operating environment, adversarial attacks, and from within the system. As a result of these concerns, human-beings lack trust in these systems and hesitate to use them for day-to-day use.In this dissertation, we develop algorithms to enhance trust by mitigating physical attacks targeting the integrity and security of sensing units of autonomous CPS. The sensors of these systems are responsible for gathering data of the physical processes. Lack of measures for securing their information can enable malicious attackers to cause life-threatening situations. This serves as a motivation for developing attack resilient solutions.Among various security solutions, attention has been recently paid toward developing system-level countermeasures for CPS whose sensor measurements are corrupted by an attacker. Our methods are along this direction as we develop an active and multiple passive algorithm to detect the attack and minimize its effect on the internal state estimates of the system. In the active approach, we leverage a challenge authentication technique for detection of two types of attacks: The Denial of Service (DoS) and the delay injection on active sensors of the systems. Furthermore, we develop a recursive least square estimator for recovery of system from attacks. The majority of the dissertation focuses on designing passive approaches for sensor attacks. In the first method, we focus on a linear stochastic system with multiple sensors, where measurements are fused in a central unit to estimate the state of the CPS. By leveraging Bayesian interpretation of the Kalman filter and combining it with the Chi-Squared detector, we recursively estimate states within an error bound and detect the DoS and False Data Injection attacks. We also analyze the asymptotic performance of the estimator and provide conditions for resilience of the state estimate.Next, we propose a novel distributed estimator based on l1 norm optimization, which could recursively estimate states within an error bound without restricting the number of agents of the distributed system that can be compromised. We also extend this estimator to a vehicle platoon scenario which is subjected to sparse attacks. Furthermore, we analyze the resiliency and asymptotic properties of both the estimators. Finally, at the end of the dissertation, we make an initial effort to formally verify the control system of the autonomous CPS using the statistical model checking method. It is done to ensure that a real-time and resource constrained system such as a self-driving car, with controllers and security solutions, adheres to strict timing constrains.
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Date Issued: 2018
Identifier: CFE0007174, ucf:52253
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007174

Title: Design and characterization of system level electrostatic discharge (ESD) protection solutions.
Creator: Xi, Yunfeng, Liou, Juin, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between 'objects' to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits...
Show moreElectrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between 'objects' to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits across existing and emerging network infrastructures. This tendency is driving an expansion in data communication as well as industrial applications environment. To keep up with the interconnectivity expansion, the industry requires new devices to support more effectively high speed signals processing over long distances and be able to reliably operate in harsh and noisy environments. Electrical over-stress transients caused by ESD or switching of inductive loads can corrupt data transmission and damage bus transceivers unless effective measures are taken to address the impact of such high energy transient stress conditions. Today's industry specifications for integrated circuits require 1kV HBM on all pins, but selected pins with direct contact to the external environment must comply with levels as high as 8kV for IEC 61000-4-2 and ISO 10605 standards. The rapid evolution of the handheld and mobile device market segment, dramatic increase of electronic content in automotive products, and substantial progress in industrial and medical applications created a new need for on-chip protection against system level ESD stresses. This PhD work investigates the impact of system-level type of ESD stress on components. Firstly, correlation factors between different ESD pulse types for different BEOL metal line topologies have been studied to support system level on-chip ESD design. The component level (HMM, HBM and TLP on wafer) and system level (IEC gun contact on package) ESD stresses were correlated followed by extraction of correlation factors between the IEC/HMM and TLP, as well as the HBM and TLP supported by analytical approximation. The major conclusions were verified using the thermal coupled mixed-mode simulations analysis. Secondly, operation of NLDMOS-SCR devices under the HMM and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, while both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such a dependency has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40ns. In the last section, a new silicon-controlled rectifier (SCR) fabricated in a 30 V mixed-signal CDMOS (CMOS/DMOS) technology is presented. This device allows for robust EMI (electromagnetic interference) and ESD (electrostatic discharge) protection solution for high speed industrial interface applications operating in variable voltage swing range from -7V to +12V. This new SCR has reduced overshoot voltage and leakage current when electrically stressed under different pulse widths and temperatures. Analysis of the device physics is complemented via numerical TCAD mixed-mode simulations. A 200 x 200 (&)#181;m2 device designed in an annular configuration achieved (>) (&)#177; 8 kV IEC robustness by handling (>) (&)#177; 20 Amp of TLP current while clamping the voltage to (&)#177;3V within 2-nsec.
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Date Issued: 2016
Identifier: CFE0006199, ucf:51113
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006199

Title: Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event.
Creator: Miao, Meng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description: In this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide...
Show moreIn this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide-Semiconductor (DMOS) process are used for design of experiment. A multi-function test platform High Power Pulse Instrument (HPPI) is used for ESD event evaluation and device characterization. SPICE-like software ADICE is for back-end simulation.Electrostatic Discharges (ESD) is one of the hazard that may affect IC circuit function and cause serious damage to the chip. The importance of ESD protection has been raised since the CMOS technology advanced and the dimension of transistors scales down. On the other hand, the variety of applications of chips is also making corresponding ESD protection difficult to meet different design requirement. Aside from typical requirements such as core circuit operation voltage, maximum accepted leakage current, breakdown conditions for the process and overall device sizes, special applications like radio frequency and power electronic requires ESD to be low parasitic capacitance and can sustain high level energy. In that case, a proper ESD protection design demands not only a robust ESD protection scheme, but co-design with the inner circuit. For that purpose, it is necessary to simulate the results of ESD impact on IC and find out possible weak point of the circuit and improve it. The first step of the simulation is to have corresponding models available. Unfortunately, ESD models, especially there are lack of circuit-level ESD models that provide quick and accurate prediction of ESD event.In this dissertation paper, ESD models, especially ESD failure models for device thermal failure are introduced, with modeling methodology accordingly. First, an introduction for ESD event and typical ESD protection schemes are introduced. Its purpose is to give basic concept of ESD. For ESD failure models, two typical types can be categorized depends on the physical mechanisms that cause the ESD damage. One is the gate oxide breakdown, which is electric field related. The other is the thermal-related failure, which stems from the self-heating effect associated with the large current passing through the ESD protection structure. The first one has become increasingly challenging with the aggressive scaling of the gate dielectric in advanced processes and ESD protection for that need to be carefully designed. The second one, thermal failure widely exists in semiconductor devices as long as there is ESD current flow through the device and accumulate heat at junctions. Considering the universality of thermal failure in ESD device, it is imperative to establish a model to simulate ESD caused thermal failure.Several works related to ESD model can be done. One crucial part for a failure model is to define the failure criterion. As common solution for ESD simulation and failure prediction. The maximum current level or breakdown voltage is used to judge whether a device fails under ESD stresses. Such failure criteria based on measurable voltage or current values are straightforward and can be easy to implemented in simulation tools. However, the shortcoming of these failure criteria is each failure criterion is specifically designed for certain ESD stress condition. For example, the failure voltage level for Human Body Model and Charged Device Model are quite different, and it is hard to judge a device's ESD capability under standard test conditions based on its transmission line pulse test result. So it is necessary to look deeper into the physical mechanism of device failure under ESD and find a more universal failure criterion for various stress conditions.As one of the major failure mechanisms, thermal failure evaluated by temperature is a more universal failure criterion for device failure under ESD stress. Whatever the stress model is, the device will fail if a critical temperature is reached at certain part inside the device and cause structural damage. Then finding out that critical temperature is crucial to define the failure point for device thermal failure. One chapter of this dissertation will focus on discussing this issue and propose a simple method to give close estimation of the real failure temperature for typical ESD devices.Combined these related works, a comprehensive diode model for ESD simulation is proposed. Using existing ESD models, diode I-V characteristic from low current turn-on to high current saturation can be simulated. By using temperature as the failure criterion, the last point of diode operation, or the second breakdown point, can be accurately predicted. Additional investigation of ESD capability of devices for special case like vertical GaN diode is discussed in Chapter IV. Due to the distinct material property of GaN, the vertical GaN diode exhibits unique and interesting quasi-static I-V curves quite different from conventional silicon semiconductor devices. And that I-V curve varies with different pulse width, indicating strong conductivity modulation of diode neutral region that will delay the complete turn-on of the vertical GaN diode.
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Date Issued: 2017
Identifier: CFE0006626, ucf:51291
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006626

Title: Design of Novel Devices and Circuits for Electrostatic Discharge Protection Applications in Advanced Semiconductor Technologies.
Creator: Wang, Zhixin, Liou, Juin, Gong, Xun, Yuan, Jiann-Shiun, Jin, Yier, Vinson, James, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD), as a subset of Electrical Overstress (EOS), was reported to be in charge of more than 35% of failure in integrated circuits (ICs). Especially in the manufacturing process, the silicon wafer turns out to be a functional ICs after numerous physical, chemical and mechanical processes, each of which expose the sensitive and fragile ICs to ESD environment. In normal end-user applications, ESD from human and machine handling, surge and spike signals in the power...
Show moreElectrostatic Discharge (ESD), as a subset of Electrical Overstress (EOS), was reported to be in charge of more than 35% of failure in integrated circuits (ICs). Especially in the manufacturing process, the silicon wafer turns out to be a functional ICs after numerous physical, chemical and mechanical processes, each of which expose the sensitive and fragile ICs to ESD environment. In normal end-user applications, ESD from human and machine handling, surge and spike signals in the power supply, and wrong supplying signals, will probably cause severe damage to the ICs and even the whole systems. Generally, ESD protections are evaluated after wafer and even system fabrication, increasing the development period and cost if the protections cannot meet customer's requirements. Therefore, it is important to design and customize robust and area-efficient ESD protections for the ICs at the early development stage. As the technologies generally scaling down, however, ESD protection clamps remain comparable area consumption in the recent years because they provide the discharging path for the ESD energy which rarely scales down. Diode is the most simple and effective device for ESD protection in ICs, but the usage is significantly limited by its low turn-on voltage. MOS devices can be triggered by a dynamic-triggered RC circuit for IOs operating at low voltage, while the one triggered by a static-triggered network, e.g., zener-resistor circuit or grounded-gate configuration, provides a high trigger voltage for high-voltage applications. However, the relatively low current discharging capability makes MOS devices as the secondary choice. Silicon-controlled rectifier (SCR) has become famous due to its high robustness and area efficiency, compared to diode and MOS. In this dissertation, a comprehensive design methodology for SCR based on simulation and measurement are presented for different advanced commercial technologies. Furthermore, an ESD clamp is designed and verified for the first time for the emerging GaN technology.For the SCR, no matter what modification is going to be made, the first concern when drawing the layout is to determine the layout geometrical style, finger width and finger number. This problem for diode and MOS device were studied in detail, so the same method was usually used in SCR. The research in this dissertation provides a closer look into the metal layout effect to the SCR, finding out the optimized robustness and minimized side-effect can be obtained by using specific layout geometry. Another concern about SCR is the relatively low turn-on speed when the IOs under protection is stressed by ESD pulses having very fast rising time, e.g., CDM and IEC 61000-4-2 pulses. On this occasion a large overshoot voltage is generated and cause damage to internal circuit component like gate oxides of MOS devices. The key determination of turn-on speed of SCR is physically investigated, followed by a novel design on SCR by directly connecting the Anode Gate and Cathode Gate to form internal trigger (DCSCR), with improved performance verified experimentally in this dissertation. The overshoot voltage and trigger voltage of the DCSCR will be significantly reduced, in return a better protection for internal circuit component is offered without scarifying neither area or robustness. Even though two SCR's with single direction of ESD current path can be constructed in reverse parallel to form bidirectional protection to pins, stand-alone bidirectional SCR (BSCR) is always desirable for sake of smaller area. The inherent high trigger voltage of BSCR that only fit in high-voltage technologies is overcome by embedding a PMOS transistor as trigger element, making it highly suitable for low-voltage ESD protection applications. More than that, this modification simultaneously introduces benefits including high robustness and low overshoot voltage.For high voltage pins, however, it presents another story for ESD designs. The high operation voltages require that a high trigger voltage and high holding voltage, so as to reduce the false trigger and latch-up risk. For several capacitive pins, the displacement current induced by a large snapback will cause severe damage to internal circuits. A novel design on SCR is proposed to minimize the snapback with adjustable trigger and holding voltage. Thanks to the additional a PIN diode, the similar high robustness and stable thermal leakage performance to SCR is maintained. For academic purpose of ESD design, it is always difficult to obtain the complete process deck in TCAD simulation because those information are highly confidential to the companies. Another challenge of using TCAD is the difficulty of maintaining the accuracy of physics models and predicting the performance of the other structures. In this dissertation a TCAD-aid ESD design methodology is used to evaluate ESD performance before the silicon shuttle.GaN is a promising material for high-voltage high-power RF application compared to the GaAs. However, distinct from GaAs, the leaky problem of the schottky junction and the lack of choice of passive/active components in GaN technology limit the ESD protection design, which will be discussed in this dissertation. However, a promising ESD protection clamp is finally developed based on depletion-mode pHEMT with adjustable trigger voltage, reasonable leakage current and high robustness.
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Date Issued: 2015
Identifier: CFE0006060, ucf:50989
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006060

Title: Deposition and characterization studies of boron carbon nitride (BCN) thin films prepared by dual target sputtering.
Creator: Prakash, Adithya, Sundaram, Kalpathy, Kapoor, Vikram, Yuan, Jiann-Shiun, Jin, Yier, Chow, Louis, University of Central Florida
Abstract / Description: As complementary metal-oxide semiconductor (CMOS) devices shrink to smaller size, the problems related to circuit performance such as critical path signal delay are becoming a pressing issue. These delays are a result of resistance and capacitance product (RC time constant) of the interconnect circuit. A novel material with reduced dielectric constants may compromise both the thermal and mechanical properties that can lead to die cracking during package and other reliability issues. Boron...
Show moreAs complementary metal-oxide semiconductor (CMOS) devices shrink to smaller size, the problems related to circuit performance such as critical path signal delay are becoming a pressing issue. These delays are a result of resistance and capacitance product (RC time constant) of the interconnect circuit. A novel material with reduced dielectric constants may compromise both the thermal and mechanical properties that can lead to die cracking during package and other reliability issues. Boron carbon nitride (BCN) compounds have been expected to combine the excellent properties of boron carbide (B4C), boron nitride (BN) and carbon nitride (C3N4), with their properties adjustable, depending on composition and structure. BCN thin film is a good candidate for being hard, dense, pore-free, low-k dielectric with values in the range of 1.9 to 2.1. Excellent mechanical properties such as adhesion, high hardness and good wear resistance have been reported in the case of sputtered BCN thin films. Problems posed by high hardness materials such as diamonds in high cutting applications and the comparatively lower hardness of c-BN gave rise to the idea of a mixed phase that can overcome these problems with a minimum compromise in its properties. A hybrid between semi-metallic graphite and insulating h-BN may show adjusted semiconductor properties. BCN exhibits the potential to control optical bandgap (band gap engineering) by atomic composition, hence making it a good candidate for electronic and photonic devices. Due to tremendous bandgap engineering capability and refractive index variability in BCN thin film, it is feasible to develop filters and mirrors for use in ultra violet (UV) wavelength region. It is of prime importance to understand process integration challenges like deposition rates, curing, and etching, cleaning and polishing during characterization of low-k films. The sputtering technique provides unique advantages over other techniques such as freedom to choose the substrate material and a uniform deposition over relatively large area. BCN films are prepared by dual target reactive magnetron sputtering from a B4C and BN targets using DC and RF powers respectively. In this work, an investigation of mechanical, optical, chemical, surface and device characterizations is undertaken. These holistic and thorough studies, will provide the insight into the capability of BCN being a hard, chemically inert, low-k, wideband gap material, as a potential leader in semiconductor and optics industry.
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Date Issued: 2016
Identifier: CFE0006378, ucf:51496
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006378

Title: Novel Computational Methods for Integrated Circuit Reverse Engineering.
Creator: Meade, Travis, Zhang, Shaojie, Jin, Yier, Orooji, Ali, Zou, Changchun, Lin, Mingjie, University of Central Florida
Abstract / Description: Production of Integrated Circuits (ICs) has been largely strengthened by globalization. System-on-chip providers are capable of utilizing many different providers which can be responsible for a single task. This horizontal structure drastically improves to time-to-market and reduces manufacturing cost. However, untrust of oversea foundries threatens to dismantle the complex economic model currently in place. Many Intellectual Property (IP) consumers become concerned over what potentially...
Show moreProduction of Integrated Circuits (ICs) has been largely strengthened by globalization. System-on-chip providers are capable of utilizing many different providers which can be responsible for a single task. This horizontal structure drastically improves to time-to-market and reduces manufacturing cost. However, untrust of oversea foundries threatens to dismantle the complex economic model currently in place. Many Intellectual Property (IP) consumers become concerned over what potentially malicious or unspecified logic might reside within their application. This logic which is inserted with the intention of causing harm to a consumer has been referred to as a Hardware Trojan (HT).To help IP consumers, researchers have looked into methods for finding HTs. Such methods tend to rely on high-level information relating to the circuit, which might not be accessible. There is a high possibility that IP is delivered in the gate or layout level. Some services and image processing methods can be leveraged to convert layout level information to gate-level, but such formats are incompatible with detection schemes that require hardware description language.By leveraging standard graph and dynamic programming algorithms a set of tools is developed that can help bridge the gap between gate-level netlist access and HT detection. To help in this endeavor this dissertation focuses on several problems associated with reverse engineering ICs. Logic signal identification is used to find malicious signals, and logic desynthesis is used to extract high level details.Each of the proposed method have their results analyzed for accuracy and runtime. It is found that method for finding logic tends to be the most difficult task, in part due to the degree of heuristic's inaccuracy. With minor improvements moderate sized ICs could have their high-level function recovered within minutes, which would allow for a trained eye or automated methods to more easily detect discrepancies within a circuit's design.
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Date Issued: 2017
Identifier: CFE0006896, ucf:51716
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006896

Title: Load-Balancing in Local and Metro-Area networks with MPTCP and OpenFlow.
Creator: Jerome, Austin, Bassiouni, Mostafa, Yuksel, Murat, Zou, Changchun, Jin, Yier, University of Central Florida
Abstract / Description: In this thesis, a novel load-balancing technique for local or metro-area traffic is proposed in mesh-style topologies. The technique uses Software Defined Networking (SDN) architecture with virtual local area network (VLAN) setups typically seen in a campus or small-to-medium enterprise environment. This was done to provide a possible solution or at least a platform to expand on for the load-balancing dilemma that network administrators face today. The transport layer protocol Multi-Path TCP ...
Show moreIn this thesis, a novel load-balancing technique for local or metro-area traffic is proposed in mesh-style topologies. The technique uses Software Defined Networking (SDN) architecture with virtual local area network (VLAN) setups typically seen in a campus or small-to-medium enterprise environment. This was done to provide a possible solution or at least a platform to expand on for the load-balancing dilemma that network administrators face today. The transport layer protocol Multi-Path TCP (MPTCP) coupled with IP aliasing is also used. The trait of MPTCP of forming multiple subflows from sender to receiver depending on the availability of IP addresses at either the sender or receiver helps to divert traffic in the subflows across all available paths. The combination of MPTCP subflows with IP aliasing enables spreading out of the traffic load across greater number of links in the network, and thereby achieving load balancing and better network utilization. The traffic formed of each subflow would be forwarded across the network based on Hamiltonian 'paths' which are created in association with each switch in the topology which are directly connected to hosts. The amount of 'paths' in the topology would also depend on the number of VLANs setup for the hosts in the topology. This segregation would allow for network administrators to monitor network utilization across VLANs and give the ability to balance load across VLANs. We have devised several experiments in Mininet, and the experimentation showed promising results with significantly better throughput and network utilization compared to cases where normal TCP was used to send traffic from source to destination. Our study clearly shows the advantages of using MPTCP for load balancing purposes in SDN type architectures and provides a platform for future research on using VLANs, SDN, and MPTCP for network traffic management.
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Date Issued: 2017
Identifier: CFE0006887, ucf:51705
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006887

Title: Transcriptional and Post-transcriptional Regulation of Gene Expression.
Creator: Ding, Jun, Hu, Haiyan, Li, Xiaoman, Zhang, Shaojie, Jin, Yier, University of Central Florida
Abstract / Description: Regulation of gene expression includes a variety of mechanisms to increase or decrease specific gene products. Gene expression can be regulated at any stage from transcription to post-transcription and it's essential to almost all living organisms, as it increases the versatility and adaptability by allowing the cell to express the needed proteins. In this dissertation, we comprehensively studied the gene regulation from both transcriptional and post-transcriptional points of view....
Show moreRegulation of gene expression includes a variety of mechanisms to increase or decrease specific gene products. Gene expression can be regulated at any stage from transcription to post-transcription and it's essential to almost all living organisms, as it increases the versatility and adaptability by allowing the cell to express the needed proteins. In this dissertation, we comprehensively studied the gene regulation from both transcriptional and post-transcriptional points of view. Transcriptional regulation is by which cells regulate the transcription from DNA to RNA, thereby directing gene activity. Transcriptional factors (TFs) play a very important role in transcriptional regulation and they are proteins that bind to specific DNA sequences (regulatory elements) to regulate the gene expression. Current studies on TF binding are still very limited and thus, it leaves much to be improved on understanding the TF binding mechanism. To fill this gap, we proposed a variety of computational methods for predicting TF binding elements, which have been proved to be more efficient and accurate compared with other existing tools such as DREME and RSAT peaks-motif. On the other hand, studying only the transcriptional gene regulation is not enough for a comprehensive understanding. Therefore, we also studied the gene regulation at the post-transcriptional level. MicroRNAs (miRNAs) are believed to post-transcriptionally regulate the expression of thousands of target mRNAs, yet the miRNA binding mechanism is still not well understood. In this dissertation, we explored both the traditional and novel features of miRNA-binding and proposed several computational models for miRNA target prediction. The developed tools outperformed the traditional microRNA target prediction methods (.e.g miRanda and TargetScan) in terms of prediction accuracy (precision, recall) and time efficiency.
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Date Issued: 2016
Identifier: CFE0006098, ucf:51197
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006098

Title: design, characterization and analysis of component level electrostatic discharge (esd) protection solutions.
Creator: Luo, Sirui, Liou, Juin, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description: Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology...
Show moreElectrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level.Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC's pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products.Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to (&)#177; 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR.Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology.ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices' performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range.
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Date Issued: 2015
Identifier: CFE0005655, ucf:50189
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005655

Title: Research on High-performance and Scalable Data Access in Parallel Big Data Computing.
Creator: Yin, Jiangling, Wang, Jun, Jin, Yier, Lin, Mingjie, Qi, GuoJun, Wang, Chung-Ching, University of Central Florida
Abstract / Description: To facilitate big data processing, many dedicated data-intensive storage systems such as Google File System(GFS), Hadoop Distributed File System(HDFS) and Quantcast File System(QFS) have been developed. Currently, the Hadoop Distributed File System(HDFS) [20] is the state-of-art and most popular open-source distributed file system for big data processing. It is widely deployed as the bedrock for many big data processing systems/frameworks, such as the script-based pig system, MPI-based...
Show moreTo facilitate big data processing, many dedicated data-intensive storage systems such as Google File System(GFS), Hadoop Distributed File System(HDFS) and Quantcast File System(QFS) have been developed. Currently, the Hadoop Distributed File System(HDFS) [20] is the state-of-art and most popular open-source distributed file system for big data processing. It is widely deployed as the bedrock for many big data processing systems/frameworks, such as the script-based pig system, MPI-based parallel programs, graph processing systems and scala/java-based Spark frameworks. These systems/applications employ parallel processes/executors to speed up data processing within scale-out clusters.Job or task schedulers in parallel big data applications such as mpiBLAST and ParaView can maximize the usage of computing resources such as memory and CPU by tracking resource consumption/availability for task assignment. However, since these schedulers do not take the distributed I/O resources and global data distribution into consideration, the data requests from parallel processes/executors in big data processing will unfortunately be served in an imbalanced fashion on the distributed storage servers. These imbalanced access patterns among storage nodes are caused because a). unlike conventional parallel file system using striping policies to evenly distribute data among storage nodes, data-intensive file systems such as HDFS store each data unit, referred to as chunk or block file, with several copies based on a relative random policy, which can result in an uneven data distribution among storage nodes; b). based on the data retrieval policy in HDFS, the more data a storage node contains, the higher the probability that the storage node could be selected to serve the data. Therefore, on the nodes serving multiple chunk files, the data requests from different processes/executors will compete for shared resources such as hard disk head and network bandwidth. Because of this, the makespan of the entire program could be significantly prolonged and the overall I/O performance will degrade.The first part of my dissertation seeks to address aspects of these problems by creating an I/O middleware system and designing matching-based algorithms to optimize data access in parallel big data processing. To address the problem of remote data movement, we develop an I/O middleware system, called SLAM, which allows MPI-based analysis and visualization programs to benefit from locality read, i.e, each MPI process can access its required data from a local or nearby storage node. This can greatly improve the execution performance by reducing the amount of data movement over network. Furthermore, to address the problem of imbalanced data access, we propose a method called Opass, which models the data read requests that are issued by parallel applications to cluster nodes as a graph data structure where edges weights encode the demands of load capacity. We then employ matching-based algorithms to map processes to data to achieve data access in a balanced fashion. The final part of my dissertation focuses on optimizing sub-dataset analyses in parallel big data processing. Our proposed methods can benefit different analysis applications with various computational requirements and the experiments on different cluster testbeds show their applicability and scalability.
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Date Issued: 2015
Identifier: CFE0006021, ucf:51008
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006021

Title: Enhanced Hardware Security Using Charge-Based Emerging Device Technology.
Creator: Bi, Yu, Yuan, Jiann-Shiun, Jin, Yier, DeMara, Ronald, Lin, Mingjie, Chow, Lee, University of Central Florida
Abstract / Description: The emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these...
Show moreThe emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these primitives based on the currently prevailing CMOS technology.However, the security provided by these primitives comes at the cost of large overheads mostly in terms of area and power consumption. The development of emerging technologies provides hardware security researchers with opportunities to utilize some of the otherwise unusable properties of emerging technologies in security applications. In this dissertation, we will include the security consideration in the overall performance measurements to fully compare the emerging devices with CMOS technology.The first approach is to leverage two emerging devices (Silicon NanoWire and Graphene SymFET) for hardware security applications. Experimental results indicate that emerging device based solutions can provide high level circuit protection with relatively lower performance overhead compared to conventional CMOS counterpart. The second topic is to construct an energy-efficient DPA-resilient block cipher with ultra low-power Tunnel FET. Current-mode logic is adopted as a circuit-level solution to countermeasure differential power analysis attack, which is mostly used in the cryptographic system. The third investigation targets on potential security vulnerability of foundry insider's attack. Split manufacturing is adopted for the protection on radio-frequency (RF) circuit design.
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Date Issued: 2016
Identifier: CFE0006264, ucf:51041
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006264

ESD (2)	+ -
SCR (2)	+ -
28nm CMOS (1)	+ -
BCN etching (1)	+ -
Boron carbon nitride (BCN) (1)	+ -

Cyber-Physical Systems Security (1)	+ -
DNA Motifs (1)	+ -
Data-Intensive (1)	+ -
Diode (1)	+ -
Distributed Systems (1)	+ -
ESD simulation (1)	+ -
Electrostatic Discharge (1)	+ -
Electrostatic discharge (1)	+ -
Emerging Device (1)	+ -
Energy-efficient (1)	+ -
Estimation Theory (1)	+ -
FTIR (1)	+ -
Formal Verification (1)	+ -
GGNMOS (1)	+ -
GaN (1)	+ -
Gate-Level Netlist (1)	+ -
Gene Regulation (1)	+ -
Hadoop Systems (1)	+ -
Hardware Trojan (1)	+ -
High-efficiency permanent magnet synchronous machinery (1)	+ -
High-performance Computing (1)	+ -
Integrated Circuit (1)	+ -
Integrated circuit (1)	+ -
Load-Balancing (1)	+ -
MicroRNA targets (1)	+ -

Jin, Yier (15)	+ -
University of Central Florida (15)	+ -
Sundaram, Kalpathy (6)	+ -
Yuan, Jiann-Shiun (6)	+ -
DeMara, Ronald (4)	+ -

Lin, Mingjie (4)	+ -
Salcedo, Javier (4)	+ -
Zhang, Shaojie (4)	+ -
Gong, Xun (3)	+ -
Liou, Juin (3)	+ -
Wang, Jun (3)	+ -
Wei, Lei (2)	+ -
Zou, Changchun (2)	+ -
Bai, Yu (1)	+ -
Bassiouni, Mostafa (1)	+ -
Bi, Yu (1)	+ -
Chow, Lee (1)	+ -
Chow, Louis (1)	+ -
Ding, Jun (1)	+ -
Dong, Yajie (1)	+ -
Dutta, Raj (1)	+ -
Fan, Deliang (1)	+ -
He, Chengyuan (1)	+ -
Hu, Haiyan (1)	+ -
Jerome, Austin (1)	+ -
Kapoor, Vikram (1)	+ -
Li, Xiaoman (1)	+ -
Liang, Wei (1)	+ -
Luo, Sirui (1)	+ -
Meade, Travis (1)	+ -

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