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Reactive Rejuvenation of CMOS Logic Paths using Self-activating Voltage Domains
Title
Reactive Rejuvenation of CMOS Logic Paths using Self-activating Voltage Domains.
Creator
Khoshavi Najafabadi, Navid, DeMara, Ronald, Yuan, Jiann-Shiun, Song, Zixia, University of Central Florida
Abstract / Description
Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to...
Show moreAggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping. Results indicate the effectiveness of power-gating on NBTI/PBTI phenomena and propose a preferred sleep transistor configuration for maximizing higher recovery. Furthermore, the aging effect can manifest itself as timing error on critical speed-paths of the circuit, if a large design guardband is not reserved. To mitigate circuit from BTI-induced aging, the Reactive Rejuvenation (RR) architectural approach is proposed which entails detection and recovery phases. The BTI impact on the critical and near critical paths performance is continuously examined through a lightweight logic circuit which asserts an error signal in the case of any timing violation in those paths. By observing the timing violation occurrence in the system, the timing-sensitive portion of the circuit is recovered from BTI through switching computations to redundant aging-critical voltage domain. The proposed technique achieves aging mitigation and reduced energy consumption as compared to a baseline circuit. Thus, signi?cant voltage guardbands to meet the desired timing speci?cation are avoided result in energy savings during circuit operation.
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Date Issued
2016
Identifier
CFE0006339, ucf:51561
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006339
Energy-Aware Data Movement In Non-Volatile Memory Hierarchies
Title
Energy-Aware Data Movement In Non-Volatile Memory Hierarchies.
Creator
Khoshavi Najafabadi, Navid, DeMara, Ronald, Yuan, Jiann-Shiun, Song, Zixia, University of Central Florida
Abstract / Description
While technology scaling enables increased density for memory cells, the intrinsic high leakagepower of conventional CMOS technology and the demand for reduced energy consumption inspiresthe use of emerging technology alternatives such as eDRAM and Non-Volatile Memory (NVM) including STT-MRAM, PCM, and RRAM. The utilization of emerging technology in Last Level Cache (LLC) designs which occupies a signi?cant fraction of total die area in Chip Multi Processors (CMPs) introduces new dimensions...
Show moreWhile technology scaling enables increased density for memory cells, the intrinsic high leakagepower of conventional CMOS technology and the demand for reduced energy consumption inspiresthe use of emerging technology alternatives such as eDRAM and Non-Volatile Memory (NVM) including STT-MRAM, PCM, and RRAM. The utilization of emerging technology in Last Level Cache (LLC) designs which occupies a signi?cant fraction of total die area in Chip Multi Processors (CMPs) introduces new dimensions of vulnerability, energy consumption, and performance delivery. To be speci?c, a part of this research focuses on eDRAM Bit Upset Vulnerability Factor (BUVF) to assess vulnerable portion of the eDRAM refresh cycle where the critical charge varies depending on the write voltage, storage and bit-line capacitance. This dissertation broaden the study on vulnerability assessment of LLC through investigating the impact of Process Variations (PV) on narrow resistive sensing margins in high-density NVM arrays, including on-chip cache and primary memory. Large-latency and power-hungry Sense Ampli?ers (SAs) have been adapted to combat PV in the past. Herein, a novel approach is proposed to leverage the PV in NVM arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time.On the other hand, this dissertation investigates a novel technique to prioritize the service to 1)Extensive Read Reused Accessed blocks of the LLC that are silently dropped from higher levelsof cache, and 2) the portion of the working set that may exhibit distant re-reference interval in L2. In particular, we develop a lightweight Multi-level Access History Pro?ler to ef?ciently identifyERRA blocks through aggregating the LLC block addresses tagged with identical Most Signi?cantBits into a single entry. Experimental results indicate that the proposed technique can reduce theL2 read miss ratio by 51.7% on average across PARSEC and SPEC2006 workloads.In addition, this dissertation will broaden and apply advancements in theories of subspace recoveryto pioneer computationally-aware in-situ operand reconstruction via the novel Logic In Intercon-nect (LI2) scheme. LI2 will be developed, validated, and re?ned both theoretically and experimentally to realize a radically different approach to post-Moore's Law computing by leveraginglow-rank matrices features offering data reconstruction instead of fetching data from main memory to reduce energy/latency cost per data movement. We propose LI2 enhancement to attain highperformance delivery in the post-Moore's Law era through equipping the contemporary micro-architecture design with a customized memory controller which orchestrates the memory requestfor fetching low-rank matrices to customized Fine Grain Recon?gurable Accelerator (FGRA) forreconstruction while the other memory requests are serviced as before. The goal of LI2 is to conquer the high latency/energy required to traverse main memory arrays in the case of LLC miss, by using in-situ construction of the requested data dealing with low-rank matrices. Thus, LI2 exchanges a high volume of data transfers with a novel lightweight reconstruction method under speci?c conditions using a cross-layer hardware/algorithm approach.
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Date Issued
2017
Identifier
CFE0006754, ucf:51859
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006754