View All Items
(1 - 3 of 3)
- Title
- China's fight for national liberation.
- Creator
-
Lin, Chen
- Date Issued
- 1938
- Identifier
- 671274, CFDT671274, ucf:5524
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/FCLA/DT/671274
- Title
- Towards High-Efficiency Data Management In the Next-Generation Persistent Memory System.
- Creator
-
Chen, Xunchao, Wang, Jun, Fan, Deliang, Lin, Mingjie, Ewetz, Rickard, Zhang, Shaojie, University of Central Florida
- Abstract / Description
-
For the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM). However, in order to mitigate the write disturbance in an MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. Furthermore, as the result of MTJ feature size scaling, the soft...
Show moreFor the sake of higher cell density while achieving near-zero standby power, recent research progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM). However, in order to mitigate the write disturbance in an MLC strategy, data stored in the soft bit must be restored back immediately after the hard bit switching is completed. Furthermore, as the result of MTJ feature size scaling, the soft bit can be expected to become disturbed by the read sensing current, thus requiring an immediate restore operation to ensure the data reliability. In this paper, we design and analyze a novel Adaptive Restore Scheme for Write Disturbance (ARS-WD) and Read Disturbance (ARS-RD), respectively. ARS-WD alleviates restoration overhead by intentionally overwriting soft bit lines which are less likely to be read. ARS-RD, on the other hand, aggregates the potential writes and restore the soft bit line at the time of its eviction from higher level cache. Both of these two schemes are based on a lightweight forecasting approach for the future read behavior of the cache block. Our experimental results show substantial reduction in soft bit line restore operations. Moreover, ARS promotes advantages of MLC to provide a preferable L2 design alternative in terms of energy, area and latency product compared to SLC STT-RAM alternatives. Whereas the popular Cell Split Mapping (CSM) for MLC STT-RAM leverages the inter-block nonuniform access frequency, the intra-block data access features remain untapped in the MLC design. Aiming to minimize the energy-hungry write request to Hard-Bit Line (HBL) and maximize the dynamic range in the advantageous Soft-Bit Line (SBL), an hybrid mapping strategy for MLC STT-RAM cache (Double-S) is advocated in the paper. Double-S couples the contemporary Cell-Split-Mapping with the novel Word-Split-Mapping (WSM). Sparse cache block detector and read depth based data allocation/ migration policy are proposed to release the full potential of Double-S.
Show less - Date Issued
- 2017
- Identifier
- CFE0006865, ucf:51751
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006865
- Title
- investigation of dual-stage high efficiency (&)density micro inverter for solar application.
- Creator
-
Chen, Lin, Batarseh, Issa, Mikhael, Wasfy, Wu, Xinzhang, Behal, Aman, Kutkut, Nasser, University of Central Florida
- Abstract / Description
-
Module integrated converters (MIC), also called micro inverter, in single phase have witnessed recent market success due to unique features (1) improved energy harvest, (2) improved system efficiency, (3) lower installation costs, (4) plug-N-play operation, (5) and enhanced flexibility and modularity. The MIC sector has grown from a niche market to mainstream, especially in the United States. Due to the fact that two-stage architecture is commonly used for single phase MIC application. A DC...
Show moreModule integrated converters (MIC), also called micro inverter, in single phase have witnessed recent market success due to unique features (1) improved energy harvest, (2) improved system efficiency, (3) lower installation costs, (4) plug-N-play operation, (5) and enhanced flexibility and modularity. The MIC sector has grown from a niche market to mainstream, especially in the United States. Due to the fact that two-stage architecture is commonly used for single phase MIC application. A DC-DC stage with maximum power point tracking to boost the output voltage of the Photovoltaic (PV) panel is employed in the first stage, DC-AC stage is used for use to connect the grid or the residential application. As well known, the cost of MIC is key issue compared to convention PV system, such as the architecture: string inverter or central inverter. A high efficiency and density DC-DC converter is proposed and dedicated for MIC application. Assuming further expansion of the MIC market, this dissertation presents the micro-inverter concept incorporated in large size PV installations such as MW-class solar farms where a three phase AC connection is employed. A high efficiency three phase MIC with two-stage ZVS operation for grid tied photovoltaic system is proposed which will reduce cost per watt, improve reliability, and increase scalability of MW-class solar farms through the development of new solar farm system architectures. This dissertation presents modeling and triple-loop control for a high efficiency three-phase four-wire inverter for use in grid-connected two-stage micro inverter applications. An average signal model based on a synchronous rotation frame for a three-phase four-wire inverter has been developed. The inner current loop consists of a variable frequency bidirectional current mode (VFBCM) controller which regulates output filter inductor current thereby achieving ZVS, improved system response, and reduced grid current THD. Active damping of the LCL output filter using filter inductor current feedback is discussed along with small signal modeling of the proposed control method. Since the DC-link capacitor plays a critical role in two-stage micro inverter applications, a DC-link controller is implemented outside of the two current control loops to keep the bus voltage constant. In the end, simulation and experimental results from a 400 watt prototype are presented to verify the validity of the theoretical analysis.
Show less - Date Issued
- 2014
- Identifier
- CFE0005148, ucf:50699
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0005148
