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DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES
Title
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
Creator
SALCEDO, Javier, Liou, Juin, University of Central Florida
Abstract / Description
The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
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Date Issued
2006
Identifier
CFE0001213, ucf:46942
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001213
Design, Simulation and Characterization of Novel Electrostatic Discharge Protection Devices and Circuits in Advanced Silicon Technologies
Title
Design, Simulation and Characterization of Novel Electrostatic Discharge Protection Devices and Circuits in Advanced Silicon Technologies.
Creator
Liang, Wei, Sundaram, Kalpathy, Fan, Deliang, Jin, Yier, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description
Electrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be...
Show moreElectrostatic Discharge (ESD) has been one of the major reliability concerns in the advanced silicon technologies and it becomes more important with technology scaling. It has been reported that more than 35% of the failures in integrated circuits (ICs) are ESD induced. ESD event is a phenomenon that a finite amount of charges transfer between two objects with different potential in a quite short time. Such event contains a large energy and the ICs without proper ESD protection could be destroyed easily, so ESD protection solutions are essential to semiconductor industry.ESD protection design consists of on-chip and off-chip ESD protection design, and the research works in this dissertation are all conducted in on-chip level, which incorporate the ESD protection devices and circuits into the microchip, to provide with basic ESD protection from manufacturing to customer use. The basic idea of ESD protection design is to provide a path with low impedance which directs most of the ESD current to flow through itself instead of the core circuit, and the ESD protection path must be robust enough to make sure that it does not fail before the core circuit. In this way, proper design on protection devices and circuits should be considered carefully. To assist the understanding and design of ESD protection, the ESD event in real world has been classified into a few ESD model including Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM), etc. Some mainstream testing method and industry standard are also introduced, including Transmission Line Pulse (TLP), and IEC 61000-4-2. ESD protection devices including diode, Gate-Grounded N-type MOSFET (GGNMOS), Silicon Controlled Rectifier (SCR) are basic elements for ESD protection design. In this dissertation, the device characteristics in ESD event and their applications are introduced. From the perspective of the whole chip ESD protection design, the concept of circuit level ESD protection and the ESD clamps are also briefly introduced. Technology Computer Aided Design (TCAD) and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation is widely used in ESD protection design. In this dissertation, TCAD and SPICE simulation are carried out for a few times for both of pre-tapeout evaluation on characteristics of the proposed device and circuit and post-tapeout analysis on structure operating mechanism.Automotive electronics has been a popular subject in semiconductor industry, and due to the special requirement of the automotive applications like the capacitive pins, the ESD protection device used in such applications need to be specially designed. In this dissertation, a few SCRs without snapback are discussed in detail. To avoid core circuit damages caused the displacement current induced by the large snapback in conventional SCR, an eliminated/minimized snapback is preferred in a selection of the protection device. Two novel SCRs are proposed for High Voltage (HV), Medium Voltage (MV), and Low Voltage (LV) automotive ESD protection.The typical operating temperature for ICs is up to 125 (&)#186;C, however in automotive applications, the operating temperature may extend up to 850 (&)#186;C. In this way, the characteristics of the ESD protection device under the elevated temperatures will be an essential part to investigate for automotive ESD protection design. In this dissertation, the high temperature characteristics of ESD protection devices including diode and a few SCRs is measured and discussed in detail. TCAD simulation are also conducted to explain the underlying physical mechanism. This work provides with a useful insight and information to ESD protection design in high temperature applications.Besides the high temperature environment, ESD protection are also highly needed for electronics working in other extreme environment like the space. Space is an environment that contains kinds of radiation source and at the same time can generate abundant ESD. The ESD adhering to the space systems could be a potential threat to the space electronics. At the same time, the characteristics of the ESD protection part especially the basic protection device used in the space electronics could be influenced after the irradiation in the space. Therefore, the investigation of the radiation effects on ESD protection devices are necessary. In this dissertation, the total ionizing dose (TID) effects on ESD protection devices are investigated. The devices are irradiated with 1.5 MeV He+ and characterized with TLP tester. The pre- and post-irradiation characteristics are compared and the variation on key ESD parameters are analyzed and discussed. This work offers a useful insight on ESD devices' operation under TID and help with the device designing on ESD protection devices for space electronics.Single ESD protection devices are essential part constructing the ESD protection network, however the optimization on ESD clamp circuit design is also important on building an efficient whole chip ESD protection network. In this dissertation, the design and simulation of a novel voltage triggered ESD detection circuit are introduced. The voltage triggered ESD detection circuit is proposed in a 0.18 um CMOS technology. Comparing with the conventional RC based detection circuit, the proposed circuit realizes a higher triggering efficiency with a much smaller footprint, and is immune to false triggering under fast power-up events. The proposed circuit has a better sensitivity to ESD event and is more reliable in ESD protection applications.The leakage current has been a concern with the scaling down of the thickness of the gate oxide. Therefore, a proper design of the ESD clamp for power rail ESD protection need to be specially considered. In this dissertation, a design of a novel ESD clamp with low leakage current is analyzed. The proposed clamp realized a pretty low leakage current up to 12 nA, and has a smaller footprint than conventional design. It also has a long hold-on time under ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the operation of the proposed ESD clamp.
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Date Issued
2017
Identifier
CFE0007126, ucf:52298
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0007126
Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies.
Title
Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies.
Creator
Dong, Aihua, Sundaram, Kalpathy, Fan, Deliang, Gong, Xun, Wei, Lei, Salcedo, Javier, University of Central Florida
Abstract / Description
Electrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to...
Show moreElectrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to FinFET technology requires more robust ESD protection however the large parasitic capacitance of ESD protection cell is problematic in high-speed interface design. To reduce the parasitic capacitance, a dual diode silicon controlled rectifier (DD-SCR) is presented in this dissertation. This design can exhibit good trade-offs between ESD robustness and parasitic capacitance characteristics. Besides, different bounding materials lead to performance variations in DD-SCRs are compared. Radio frequency (RF) technology is also demanded low capacitance ESD protection. To address this concern, a ?-network is presented, providing robust ESD protection for 10-60 GHz RF circuit. Like a low pass ? filter, the network can reflect high frequency RF signals and transmit low frequency ESD pulses. Given proper inductor value, networks can work as robust ESD solutions at a certain Giga Hertz frequency range, making this design suitable for broad band protection in RF input/outputs (I/Os). To increase the holding voltage and reduce snapback, a resistor assist triggering heterogeneous stacking structure is presented in this dissertation, which can increase the holding voltage and also keep the trigger voltage nearly as same as a single SCR device.
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Date Issued
2018
Identifier
CFE0007172, ucf:52251
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0007172
Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions
Title
Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions.
Creator
Li, Hang, Sundaram, Kalpathy, Batarseh, Issa, Fan, Deliang, Gong, Xun, Salcedo, Javier, University of Central Florida
Abstract / Description
Electrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A...
Show moreElectrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A compact model is developed to predict thermal failure with circuit simulators. Instead of considering the detailed failure mechanisms, a failure temperature is introduced to indicate device failure. The developed model is implemented by a multiple-stage thermal network.P-N junction is the fundamental structure for ESD protection devices. An enhanced diode model is proposed and is used to simulate the device behaviors for ESD events. The model includes all physical effects for ESD conditions, which are voltage overshoot, self-heating effect, velocity saturation and thermal failure. The proposed model not only can fit the I-V and transient characteristics, but also can predict failure for different pulses.Safe Operating Area (SOA) is an important factor to evaluate the LDMOS performance. The transient SOA boundary is considered as power-defined. By placing the failure monitor under certain conditions, the developed modeling methodology can predict the boundary of transient SOA for any short pulse stress conditions. No matter failure happens before or after snapback phenomenon.Weibull distribution is popular to evaluate the dielectric lifetime for CVS. By using the transformative version of power law, the pulsing stresses are converted into CVS, and TDDB under ESD conditions for SiN MIMCAPs is analyzed. The thickness dependency and area independency of capacitor breakdown voltage is observed, which can be explained by the constant ?E model instead of conventional percolation model.
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Date Issued
2019
Identifier
CFE0007670, ucf:52512
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0007670
Design and characterization of system level electrostatic discharge (ESD) protection solutions
Title
Design and characterization of system level electrostatic discharge (ESD) protection solutions.
Creator
Xi, Yunfeng, Liou, Juin, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description
Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between 'objects' to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits...
Show moreElectrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between 'objects' to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits across existing and emerging network infrastructures. This tendency is driving an expansion in data communication as well as industrial applications environment. To keep up with the interconnectivity expansion, the industry requires new devices to support more effectively high speed signals processing over long distances and be able to reliably operate in harsh and noisy environments. Electrical over-stress transients caused by ESD or switching of inductive loads can corrupt data transmission and damage bus transceivers unless effective measures are taken to address the impact of such high energy transient stress conditions. Today's industry specifications for integrated circuits require 1kV HBM on all pins, but selected pins with direct contact to the external environment must comply with levels as high as 8kV for IEC 61000-4-2 and ISO 10605 standards. The rapid evolution of the handheld and mobile device market segment, dramatic increase of electronic content in automotive products, and substantial progress in industrial and medical applications created a new need for on-chip protection against system level ESD stresses. This PhD work investigates the impact of system-level type of ESD stress on components. Firstly, correlation factors between different ESD pulse types for different BEOL metal line topologies have been studied to support system level on-chip ESD design. The component level (HMM, HBM and TLP on wafer) and system level (IEC gun contact on package) ESD stresses were correlated followed by extraction of correlation factors between the IEC/HMM and TLP, as well as the HBM and TLP supported by analytical approximation. The major conclusions were verified using the thermal coupled mixed-mode simulations analysis. Secondly, operation of NLDMOS-SCR devices under the HMM and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, while both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such a dependency has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40ns. In the last section, a new silicon-controlled rectifier (SCR) fabricated in a 30 V mixed-signal CDMOS (CMOS/DMOS) technology is presented. This device allows for robust EMI (electromagnetic interference) and ESD (electrostatic discharge) protection solution for high speed industrial interface applications operating in variable voltage swing range from -7V to +12V. This new SCR has reduced overshoot voltage and leakage current when electrically stressed under different pulse widths and temperatures. Analysis of the device physics is complemented via numerical TCAD mixed-mode simulations. A 200 x 200 (&)#181;m2 device designed in an annular configuration achieved (>) (&)#177; 8 kV IEC robustness by handling (>) (&)#177; 20 Amp of TLP current while clamping the voltage to (&)#177;3V within 2-nsec.
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Date Issued
2016
Identifier
CFE0006199, ucf:51113
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006199
Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event
Title
Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event.
Creator
Miao, Meng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description
In this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide...
Show moreIn this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide-Semiconductor (DMOS) process are used for design of experiment. A multi-function test platform High Power Pulse Instrument (HPPI) is used for ESD event evaluation and device characterization. SPICE-like software ADICE is for back-end simulation.Electrostatic Discharges (ESD) is one of the hazard that may affect IC circuit function and cause serious damage to the chip. The importance of ESD protection has been raised since the CMOS technology advanced and the dimension of transistors scales down. On the other hand, the variety of applications of chips is also making corresponding ESD protection difficult to meet different design requirement. Aside from typical requirements such as core circuit operation voltage, maximum accepted leakage current, breakdown conditions for the process and overall device sizes, special applications like radio frequency and power electronic requires ESD to be low parasitic capacitance and can sustain high level energy. In that case, a proper ESD protection design demands not only a robust ESD protection scheme, but co-design with the inner circuit. For that purpose, it is necessary to simulate the results of ESD impact on IC and find out possible weak point of the circuit and improve it. The first step of the simulation is to have corresponding models available. Unfortunately, ESD models, especially there are lack of circuit-level ESD models that provide quick and accurate prediction of ESD event.In this dissertation paper, ESD models, especially ESD failure models for device thermal failure are introduced, with modeling methodology accordingly. First, an introduction for ESD event and typical ESD protection schemes are introduced. Its purpose is to give basic concept of ESD. For ESD failure models, two typical types can be categorized depends on the physical mechanisms that cause the ESD damage. One is the gate oxide breakdown, which is electric field related. The other is the thermal-related failure, which stems from the self-heating effect associated with the large current passing through the ESD protection structure. The first one has become increasingly challenging with the aggressive scaling of the gate dielectric in advanced processes and ESD protection for that need to be carefully designed. The second one, thermal failure widely exists in semiconductor devices as long as there is ESD current flow through the device and accumulate heat at junctions. Considering the universality of thermal failure in ESD device, it is imperative to establish a model to simulate ESD caused thermal failure.Several works related to ESD model can be done. One crucial part for a failure model is to define the failure criterion. As common solution for ESD simulation and failure prediction. The maximum current level or breakdown voltage is used to judge whether a device fails under ESD stresses. Such failure criteria based on measurable voltage or current values are straightforward and can be easy to implemented in simulation tools. However, the shortcoming of these failure criteria is each failure criterion is specifically designed for certain ESD stress condition. For example, the failure voltage level for Human Body Model and Charged Device Model are quite different, and it is hard to judge a device's ESD capability under standard test conditions based on its transmission line pulse test result. So it is necessary to look deeper into the physical mechanism of device failure under ESD and find a more universal failure criterion for various stress conditions.As one of the major failure mechanisms, thermal failure evaluated by temperature is a more universal failure criterion for device failure under ESD stress. Whatever the stress model is, the device will fail if a critical temperature is reached at certain part inside the device and cause structural damage. Then finding out that critical temperature is crucial to define the failure point for device thermal failure. One chapter of this dissertation will focus on discussing this issue and propose a simple method to give close estimation of the real failure temperature for typical ESD devices.Combined these related works, a comprehensive diode model for ESD simulation is proposed. Using existing ESD models, diode I-V characteristic from low current turn-on to high current saturation can be simulated. By using temperature as the failure criterion, the last point of diode operation, or the second breakdown point, can be accurately predicted. Additional investigation of ESD capability of devices for special case like vertical GaN diode is discussed in Chapter IV. Due to the distinct material property of GaN, the vertical GaN diode exhibits unique and interesting quasi-static I-V curves quite different from conventional silicon semiconductor devices. And that I-V curve varies with different pulse width, indicating strong conductivity modulation of diode neutral region that will delay the complete turn-on of the vertical GaN diode.
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Date Issued
2017
Identifier
CFE0006626, ucf:51291
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006626
design, characterization and analysis of component level electrostatic discharge (esd) protection solutions
Title
design, characterization and analysis of component level electrostatic discharge (esd) protection solutions.
Creator
Luo, Sirui, Liou, Juin, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description
Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology...
Show moreElectrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level.Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC's pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products.Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to (&)#177; 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR.Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology.ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices' performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range.
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Date Issued
2015
Identifier
CFE0005655, ucf:50189
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0005655