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MODELING,DESIGN,AND CHARACTERIZATION OF MONOLITHIC BI-DIRECTIONAL POWER SEMICONDUCTOR SWITCH
Title
MODELING,DESIGN,AND CHARACTERIZATION OF MONOLITHIC BI-DIRECTIONAL POWER SEMICONDUCTOR SWITCH.
Creator
Fu, Yue, Shen, Z.John, University of Central Florida
Abstract / Description
Bidirectional power switching devices are needed in many power management applications, particularly in lithium-ion battery protection circuitry. A monolithic bidirectional power switch fabricated with a simplified CMOS technology is introduced in this dissertation. Throughout the design process, ISE TCAD tool plays an important role. Design variables are carefully analyzed to improve the device performance or yield the best trade off. Optimization is done with the help of TCAD simulation and...
Show moreBidirectional power switching devices are needed in many power management applications, particularly in lithium-ion battery protection circuitry. A monolithic bidirectional power switch fabricated with a simplified CMOS technology is introduced in this dissertation. Throughout the design process, ISE TCAD tool plays an important role. Design variables are carefully analyzed to improve the device performance or yield the best trade off. Optimization is done with the help of TCAD simulation and theoretical calculations. The device has been successfully fabricated using simplified 0.5 micron CMOS process. The experimental result shows a breakdown voltage of 25V. Due to the interdigitated source to source design, the inter-terminal current flowing path is effectively reduced to a few microns. The experimental result shows an ultra low specific on resistance. In comparison with other bi-directional power semiconductor switches by some major semiconductor manufacturers, the proposed BDS device has less than one half of the specific on resistance, thus substantially lower on state power loss of the switch. The proposed BDS device has a unique NPNPN structure, in comparison with NPNP structure, which is the analytical structure for CMOS latch-up, the proposed device inherently exhibits a better latch up immunity than CMOS inverter, thanks to the negative feed back mechanism of the extra NPN parasitic BJT transistor. In order to implement the device into simulators like PSPICE or Cadence IC Design, a compact model named variable resistance model has been built. This simple analytical model fits quite well with experimental data, and can be easily implemented by Verilog-A or other hardware description languages. Also, macro modeling is possible provided that the model parameters can be extracted from experimental curves. Several advanced types of BDS devices have been proposed, they exceed the basic BDS design in terms of breakdown voltage and /or on resistance. These advanced structures may be prominent for further improvement of the basic BDS device to a higher extend. Some cell phone providers such as Nokia is already asking for higher breakdown voltage of BDS device, due to the possibility of incidentally insert the battery pack into the cell phone with wrong pin polarity. Hopefully, the basic BDS design or one of these advanced types may eventually be implemented into the leading brand cell phone battery packs.
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Date Issued
2007
Identifier
CFE0001605, ucf:47168
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001605
DESIGN AND MODELING OF RADIATION HARDENED LDMOSFET FOR SPACE CRAFT POWER SYSTEMS
Title
DESIGN AND MODELING OF RADIATION HARDENED LDMOSFET FOR SPACE CRAFT POWER SYSTEMS.
Creator
Shea, Patrick, Shen, John, University of Central Florida
Abstract / Description
NASA missions require innovative power electronics system and component solutions with long life capability, high radiation tolerance, low mass and volume, and high reliability in space environments. Presently vertical double-diffused MOSFETs (VDMOS) are the most widely used power switching device for space power systems. It is proposed that a new lateral double-diffused MOSFET (LDMOS) designed at UCF can offer improvements in total dose and single event radiation hardness, switching...
Show moreNASA missions require innovative power electronics system and component solutions with long life capability, high radiation tolerance, low mass and volume, and high reliability in space environments. Presently vertical double-diffused MOSFETs (VDMOS) are the most widely used power switching device for space power systems. It is proposed that a new lateral double-diffused MOSFET (LDMOS) designed at UCF can offer improvements in total dose and single event radiation hardness, switching performance, development and manufacturing costs, and total mass of power electronics systems. Availability of a hardened fast-switching power MOSFET will allow space-borne power electronics to approach the current level of terrestrial technology, thereby facilitating the use of more modern digital electronic systems in space. It is believed that the use of a p+/p-epi starting material for the LDMOS will offer better hardness against single-event burnout (SEB) and single-event gate rupture (SEGR) when compared to vertical devices fabricated on an n+/n-epi material. By placing a source contact on the bottom-side of the p+ substrate, much of the hole current generated by a heavy ion strike will flow away from the dielectric gate, thereby reducing electrical stress on the gate and decreasing the likelihood of SEGR. Similarly, the device is hardened against SEB by the redirection of hole current away from the base of the device's parasitic bipolar transistor. Total dose hardness is achieved by the use of a standard complementary metal-oxide semiconductor (CMOS) process that has shown proven hardness against total dose radiation effects.
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Date Issued
2007
Identifier
CFE0001966, ucf:47468
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001966
HIGH TEMPERATURE PACKAGING FOR WIDE BANDGAP SEMICONDUCTOR DEVICES
Title
HIGH TEMPERATURE PACKAGING FOR WIDE BANDGAP SEMICONDUCTOR DEVICES.
Creator
Grummel, Brian, Shen, Z. John, University of Central Florida
Abstract / Description
Currently, wide bandgap semiconductor devices feature increased efficiency, higher current handling capabilities, and higher reverse blocking voltages than silicon devices while recent fabrication advances have them drawing near to the marketplace. However these new semiconductors are in need of new packaging that will allow for their application in several important uses including hybrid electrical vehicles, new and existing energy sources, and increased efficiency in multiple new and...
Show moreCurrently, wide bandgap semiconductor devices feature increased efficiency, higher current handling capabilities, and higher reverse blocking voltages than silicon devices while recent fabrication advances have them drawing near to the marketplace. However these new semiconductors are in need of new packaging that will allow for their application in several important uses including hybrid electrical vehicles, new and existing energy sources, and increased efficiency in multiple new and existing technologies. Also, current power module designs for silicon devices are rife with problems that must be enhanced to improve reliability. This thesis introduces new packaging that is thermally resilient and has reduced mechanical stress from temperature rise that also provides increased circuit lifetime and greater reliability for continued use to 300°C which is within operation ratings of these new semiconductors. The new module is also without problematic wirebonds that lead to a majority of traditional module failures which also introduce parasitic inductance and increase thermal resistance. Resultantly, the module also features a severely reduced form factor in mass and volume.
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Date Issued
2008
Identifier
CFE0002482, ucf:47690
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002482
MODELING AND OPTIMIZATION OF BODY DIODE REVERSE RECOVERY CHARACTERISTICS OF LDMOS TRANSISTORS
Title
MODELING AND OPTIMIZATION OF BODY DIODE REVERSE RECOVERY CHARACTERISTICS OF LDMOS TRANSISTORS.
Creator
Deschaine, Wesley, Shen, John, University of Central Florida
Abstract / Description
As switching speeds for DC-DC converter applications keep becoming faster and faster and voltage requirements become smaller and smaller, the need for new device structures becomes more prevalent. Designers of these new structures will need to make sure they take into consideration the different power losses associated with the different structures and make modifications to reduce or if possible eliminate them. A new 30V LDMOS device has been created and is being implemented into a...
Show moreAs switching speeds for DC-DC converter applications keep becoming faster and faster and voltage requirements become smaller and smaller, the need for new device structures becomes more prevalent. Designers of these new structures will need to make sure they take into consideration the different power losses associated with the different structures and make modifications to reduce or if possible eliminate them. A new 30V LDMOS device has been created and is being implemented into a synchronous buck converter for future DC-DC conversions. This new lateral device has a Figure of Merit of 80mÙ*nC, representing a 50% reduction from the conventional trench MOSFET. The only draw back with this new device is that the body diode power loss has increased significantly. There are two principal goals of this research. The first is to reduce the body diode reverse recovery characteristics of a 30V LDMOS transistor without employing an additional Schottky diode, increasing the Figure of Merit, or decreasing the breakdown voltage past 30 volts. The second is to achieve 75% reduction in reverse recovery charge (Qrr) through each solution. Four solutions will be presented in this study and have been verified through extensive ISE-TCAD device and circuit simulation.
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Date Issued
2006
Identifier
CFE0001081, ucf:46778
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001081
EMBEDDED MAGNETICS FOR POWER SYSTEM ON CHIP (PSOC)
Title
EMBEDDED MAGNETICS FOR POWER SYSTEM ON CHIP (PSOC).
Creator
Lu, Jian, Shen, Z. John, University of Central Florida
Abstract / Description
A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor...
Show moreA novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor concept. Transformer parameters including self- and mutual inductance, and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SoC manufacturing processes with minimal changes to the layout, and open enormous possibilities for realizing cost-effective, high current, high efficiency PSoC's or PSiP's. The design guidelines for single bondwire inductors as well as multi-turn inductors are discussed step by step in several chapters. Not only is the innovated concept for bondwire inductor with ferrite ink presented, but also the practical implementation and design rules are given. With all the well defined steps, people who want to use these bondwire inductors with ferrite ink in their PSoC research or products will find it as simple as using commercial inductors. Last but not least, the PSoC concept using a bondwire inductor is demonstrated by building the prototype of dc-dc buck converter IC as well as the whole package. IC and the whole function block are tested and presented in this work.
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Date Issued
2009
Identifier
CFE0002952, ucf:47953
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002952
MODELING AND ANALYSIS OF POWER MOSFETS FOR HIGH FREQUENCY DC-DC CONVERTERS
Title
MODELING AND ANALYSIS OF POWER MOSFETS FOR HIGH FREQUENCY DC-DC CONVERTERS.
Creator
Xiong, Yali, Shen, John, University of Central Florida
Abstract / Description
Evolutions in integrated circuit technology require the use of a high-frequency synchronous buck converter in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency operation leads to increased power MOSFET switching losses. Optimization of the MOSFETs plays an important role in improving converter performance. This dissertation focuses on revealing the power loss mechanism of power MOSFETs and the relationship between power MOSFET...
Show moreEvolutions in integrated circuit technology require the use of a high-frequency synchronous buck converter in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency operation leads to increased power MOSFET switching losses. Optimization of the MOSFETs plays an important role in improving converter performance. This dissertation focuses on revealing the power loss mechanism of power MOSFETs and the relationship between power MOSFET structure and its power loss. The analytical device model, combined with circuit modeling, cannot reveal the relationship between device structure and its power loss due to the highly non-linear characteristics of power MOSFETs. A physically-based mixed device/circuit modeling approach is used to investigate the power losses of the MOSFETs under different operating conditions. The physically based device model, combined with SPICE-like circuit simulation, provides an expeditious and inexpensive way of evaluating and optimizing circuit and device concepts. Unlike analytical or other SPICE models of power MOSFETs, the numerical device model, relying little on approximations or simplifications, faithfully represents the behavior of realistic power MOSFETs. The impact of power MOSFET parameters on efficiency of synchronous buck converters, such as gate charge, on resistance, reverse recovery, is studied in detail in this thesis. The results provide a good indication on how to optimize power MOSFETs used in VRMs. The synchronous rectifier plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact SyncFET's performance. This thesis gives a detailed analysis of the SyncFET operation mechanism and provides several techniques to reduce its body-diode influence and suppress its false Cdv/dt trigger-n. This thesis also investigates the influence of several circuit level parameters on the efficiency of the synchronous buck converter, such as input voltage, circuit parasitic inductance, and gate resistance to provide further optimization of synchronous buck converter design.
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Date Issued
2008
Identifier
CFE0002278, ucf:47858
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002278
POWER METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH STRAINED SILICON AND SILICON GERMANIUM CHANNEL
Title
POWER METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH STRAINED SILICON AND SILICON GERMANIUM CHANNEL.
Creator
Sun, Shan, Shen, John, University of Central Florida
Abstract / Description
With the development of modern electronics, the demand for high quality power supplies has become more urgent than ever. For power MOSFETs, maintaining the trend of reducing on-state resistance (conduction loss) without sacrificing switching performance is a severe challenge. In this work, our research is focused on implementing strained silicon and silicon germanium in power MOFETs to enhance carrier mobility, thus achieving the goal of reducing specific on-state resistance. We propose an N...
Show moreWith the development of modern electronics, the demand for high quality power supplies has become more urgent than ever. For power MOSFETs, maintaining the trend of reducing on-state resistance (conduction loss) without sacrificing switching performance is a severe challenge. In this work, our research is focused on implementing strained silicon and silicon germanium in power MOFETs to enhance carrier mobility, thus achieving the goal of reducing specific on-state resistance. We propose an N-channel super-lattice trench MOSFET, a P-channel sidewall channel trench MOSFET and P-Channel LDMOS with strained Si/SiGe channels. A set of fabrication processes highly compatible with conventional Si technology is developed to fabricate proposed devices. The mobility enhancement is observed to be 20%, 40% and 35% respectively for N-channel, P-channel trench MOSFET and LDMOS respectively and the on-state resistance is reduced by 10%, 20% and 22% without sacrificing other device performance parameters.
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Date Issued
2010
Identifier
CFE0003427, ucf:48415
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003427