Current Search: Shen, Zheng (x)
View All Items
(1 - 11 of 11)
- Title
- DESIGN AND MODELING OF RADIATION HARDENED LATERAL POWER MOSFETS.
- Creator
-
Landowski, Matthew, Shen, Zheng, University of Central Florida
- Abstract / Description
-
Galactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated...
Show moreGalactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated mix of photo-generated current, avalanche generated current, and activation of the inherent parasitic bipolar transistor. Current space-borne power systems lack the utility and advantages of terrestrial power systems. Vertical-double-diffused MOSFETs (VDMOS) is by far the most common power semiconductor device and are very susceptible to SEEs by their vertical structure. Modern space power switches typically require system designers to de-rate the power semiconductor switching device to account for this. Consequently, the power system suffers from increased size, cost, and decreased performance. Their switching speed is limited due to their vertical structure and cannot be used for MHz frequency applications limiting the use of modern digital electronics for space missions. Thus, the Power Semiconductor Research Laboratory at the University of Central Florida in conjunction with Sandia National Laboratories is developing a rad-hard by design lateral-double-diffused MOSFET (LDMOS). The study provides a novel in-depth physical analysis of the mechanisms that cause the LDMOS to burnout during an SEE and provides guidelines for making the LDMOS rad-hard to SEB. Total dose radiation, another important radiation effect, can cause threshold voltage shifts but is beyond the scope of this study. The devices presented have been fabricated with a known total dose radiation hard CMOS process. Single-event burnout data from simulations and experiments are presented in the study to prove the viability of using the LDMOS to replace the VDMOS for space power systems. The LDMOS is capable of higher switching speeds due to a reduced drain-gate feedback capacitance (Miller Capacitor). Since the device is lateral it is compatible with complimentary-metal-oxide-semiconductor (CMOS) processes, lowering developing time and fabrication costs. High switching frequencies permit the use of high density point-of-load conversion and provide a fast dynamic response.
Show less - Date Issued
- 2009
- Identifier
- CFE0002795, ucf:48113
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002795
- Title
- Lateral Power MOSFETs Hardened Against Single Event Radiation Effects.
- Creator
-
Shea, Patrick, Shen, Zheng, Yuan, Jiann-Shiun, Malocha, Donald, University of Central Florida
- Abstract / Description
-
The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard...
Show moreThe underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metrics.
Show less - Date Issued
- 2011
- Identifier
- CFE0004165, ucf:49044
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004165
- Title
- Design and Characterization of High Temperature Packaging for Wide-Bandgap Semiconductor Devices.
- Creator
-
Grummel, Brian, Shen, Zheng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
-
Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor...
Show moreAdvances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au(-)In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au(-)In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermo-mechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.
Show less - Date Issued
- 2012
- Identifier
- CFE0004499, ucf:49276
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004499
- Title
- A NEW QUASI RESONANT DC-LINK FOR PHOTOVOLTAIC MICRO-INVERTERS.
- Creator
-
Grishina, Anna, Batarseh, Issa, Shen, Zheng, Kutkut, Nasser, University of Central Florida
- Abstract / Description
-
PV Inverters have the task of tracking the maximum power point (MPP), and regulating the solar energy generation to this optimal operation point. The second task is the conversion of direct current produced by the solar modules into alternating current compatible with the grid.A new inverter approach such as a single phase micro inverter is emerging aimed to overcome some of the challenges of centralized inverters. As a counterpart to the central inverter, a micro inverter is a small compact...
Show morePV Inverters have the task of tracking the maximum power point (MPP), and regulating the solar energy generation to this optimal operation point. The second task is the conversion of direct current produced by the solar modules into alternating current compatible with the grid.A new inverter approach such as a single phase micro inverter is emerging aimed to overcome some of the challenges of centralized inverters. As a counterpart to the central inverter, a micro inverter is a small compact module attached directly to each solar panel.To provide for the constantly increasing demand for a small size, light weight and high efficiency micro inverter, soft switching power conversion technologies have been employed. The switching stress can be minimized by turning on/off each switch when the voltage across it or the current through it is zero at the switching transition. With the addition of auxiliary circuits such as auxiliary switches and LC resonant components the so called soft switching condition can be achieved for semiconductor devices.Four main purposes to investigate the soft switching technologies for single-phase micro-inverter are:(1) to improve overall efficiency by creating the favorable operating conditions for power devices using soft-switching techniques;(2) to shrink the reactive components by pushing the switching frequency to a higher range with decent efficiency.(3) to ensure soft switching does not exacerbate inverter performance, meaning all conventional PWM algorithms can be applied in order to meet IEEE standards.(4) to investigate which soft switching techniques offer the cheapest topology and control strategy as cost and simple control are crucial for low power inverter applications.An overview on the existing soft-switching inverter topologies for single phase inverter technology is summarized.A new quasi resonant DC link that allows for pulse- width- modulation (PWM) is presented in this thesis. The proposed quasi resonant DC link provides zero-voltage switching (ZVS) condition for the main devices by resonating the DC-link voltage to zero via three auxiliary switches and LC components. The operating principle and mode analysis are given. The simulation was carried out to verify the proposed soft switching technique. A 150W 120VAC single-phase prototype was built. The experimental results show that the soft switching for four main switches can be realized under different load conditions and the peak efficiency can reach 95.6%. The proposed quasi DC link can be applied to both single-phase and three-phase DC/AC micro inverter.In order to boost efficiency and increase power density it is important to evaluate the power loss mechanism in each stage of operation of the micro inverter. Using the datasheet parameters of the commercially available semiconductor switches, conduction and switching losses were estimated. This thesis presents a method to analyze power losses of the new resonant DC link inverter which alleviates topology optimization and MOSFET selection. An analytical, yet simple model for calculating the conduction and switching losses was developed. With this model a rough calculation of efficiency can be done, which helps to speed up the design process and to increase efficiency.
Show less - Date Issued
- 2012
- Identifier
- CFE0004379, ucf:49397
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004379
- Title
- Design, Characterization and Analysis of Electrostatic Discharge (ESD) Protection Solutions in Emerging and Modern Technologies.
- Creator
-
Liu, Wen, Liou, Juin, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Chen, Quanfang, University of Central Florida
- Abstract / Description
-
Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and...
Show moreElectrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal(-)oxide(-)semiconductor (CMOS) technologies.The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diode-triggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end.
Show less - Date Issued
- 2012
- Identifier
- CFE0004571, ucf:49199
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004571
- Title
- Analysis and Design Optimization of Resonant DC-DC Converters.
- Creator
-
Fang, Xiang, Shen, Zheng, Batarseh, Issa, Mikhael, Wasfy, Wu, Xinzhang, Kutkut, Nasser, University of Central Florida
- Abstract / Description
-
The development in power conversion technology is in constant demand of high power efficiency and high power density. The DC-DC power conversion is an indispensable stage for numerous power supplies and energy related applications. Particularly, in PV micro-inverters and front-end converter of power supplies, great challenges are imposed on the power performances of the DC-DC converter stage, which not only require high efficiency and density but also the capability to regulate a wide...
Show moreThe development in power conversion technology is in constant demand of high power efficiency and high power density. The DC-DC power conversion is an indispensable stage for numerous power supplies and energy related applications. Particularly, in PV micro-inverters and front-end converter of power supplies, great challenges are imposed on the power performances of the DC-DC converter stage, which not only require high efficiency and density but also the capability to regulate a wide variation range of input voltage and load conditions. The resonant DC-DC converters are good candidates to meet these challenges with the advantages of achieving soft switching and low EMI. Among the resonant converters, the LLC converter is very attractive for its high gain range and providing ZVS from full load to zero load condition. The operation of the LLC converter is complicated due to its multiple resonant stage mechanism. In this dissertation, a literature review of different analysis methods are presented, and it shows that the study on the LLC is still incomplete. Therefore, an operation mode analysis method is proposed, which divides the operation into six major modes based on the occurrence of resonant stages. The resonant currents, voltages and the DC gain characteristics for each mode is investigated. To get a thorough view of the converter behavior, the boundaries of every mode are studied, and the mode distribution is discussed. An experimental prototype is built and tested to demonstrate its accuracy in operation waveforms and gain prediction. Since most of the LLC modes have no closed-form solutions, simplification is necessary in order to utilize this mode model in practical design. As the peak gain is an important design parameters indicating the LLC's operating limit of input voltage and switching frequency, a numerical peak gain approximation method is developed, which provide a direct way to calculate the peak gain and its corresponding load and frequency condition. In addition, as PO mode is the most favorable operation mode of the LLC, its operation region is investigated and an approximation approach is developed to determine its boundary. The design optimization of the LLC has always been a difficult problem as there are many parameters affecting the design and it lacks clear design guidance in selecting the optimal resonant tank parameters. Based on the operation mode model, three optimization methods are proposed according to the design scenarios. These methods focus on minimize the conduction loss of resonant tank while maintaining the required voltage gain level, and the approximations of peak gains and mode boundary can be applied here to facilitate the design. A design example is presented following one of the optimization procedure. As a comparison, the L-C component values are reselected and tested while the design specifications are the same. The experiments show that the optimal design has better efficiency performance. Finally, a generalized approach for resonant converter analysis is developed. It can be implemented by computer programs or numerical analysis tools to derive the operation waveforms and DC characteristics of resonant converters.
Show less - Date Issued
- 2012
- Identifier
- CFE0004229, ucf:49026
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004229
- Title
- Transient Safe Operating Area (TSOA) for ESD applications.
- Creator
-
Malobabic, Slavica, Liou, Juin, Shen, Zheng, Yuan, Jiann-Shiun, Vinson, James, University of Central Florida
- Abstract / Description
-
A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD).A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins.The methodology for input pins includes...
Show moreA methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD).A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins.The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs.The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identified.
Show less - Date Issued
- 2012
- Identifier
- CFE0004405, ucf:49363
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004405
- Title
- Optimization and design of photovoltaic micro-inverter.
- Creator
-
Zhang, Qian, Batarseh, Issa, Shen, Zheng, Wu, Xinzhang, Lotfifard, Saeed, Kutkut, Nasser, University of Central Florida
- Abstract / Description
-
To relieve energy shortage and environmental pollution issues, renewable energy, especially PV energy has developed rapidly in the last decade. The micro-inverter systems, with advantages in dedicated PV power harvest, flexible system size, simple installation, and enhanced safety characteristics are the future development trend of the PV power generation systems. The double-stage structure which can realize high efficiency with nice regulated sinusoidal waveforms is the mainstream for the...
Show moreTo relieve energy shortage and environmental pollution issues, renewable energy, especially PV energy has developed rapidly in the last decade. The micro-inverter systems, with advantages in dedicated PV power harvest, flexible system size, simple installation, and enhanced safety characteristics are the future development trend of the PV power generation systems. The double-stage structure which can realize high efficiency with nice regulated sinusoidal waveforms is the mainstream for the micro-inverter.This thesis studied a double stage micro-inverter system. Considering the intermittent nature of PV power, a PFC was analyzed to provide additional electrical power to the system. When the solar power is less than the load required, PFC can drag power from the utility grid.In the double stage micro-inverter, the DC/DC stage was realized by a LLC converter, which could realize soft switching automatically under frequency modulation. However it has a complicated relationship between voltage gain and load. Thus conventional variable step P(&)O MPPT techniques for PWM converter were no longer suitable for the LLC converter. To solve this problem, a novel MPPT was proposed to track MPP efficiently. Simulation and experimental results verified the effectiveness of the proposed MPPT.The DC/AC stage of the micro-inverter was realized by a BCM inverter. With duty cycle and frequency modulation, ZVS was achieved through controlling the inductor current bi-directional in every switching cycle. This technique required no additional resonant components and could be employed for low power applications on conventional full-bridge and half-bridge inverter topologies. Three different current mode control schemes were derived from the basic theory of the proposed technique. They were referred to as Boundary Current Mode (BCM), Variable Hysteresis Current Mode (VHCM), and Constant Hysteresis Current Mode (CHCM) individually in this paper with their advantages and disadvantages analyzed in detail. Simulation and experimental results demonstrated the feasibilities of the proposed soft-switching technique with the digital control schemes.The PFC converter was applied by a single stage biflyback topology, which combined the advantages of single stage PFC and flyback topology together, with further advantages in low intermediate bus voltage and current stresses. A digital controller without current sampling requirement was proposed based on the specific topology. To reduce the voltage spike caused by the leakage inductor, a novel snubber cell combining soft switching technique with snubber technique together was proposed. Simulation and experimental waveforms illustrated the same as characteristics as the theoretical analysis.In summary, the dissertation analyzed each power stage of photovoltaic micro-inverter system from efficiency and effectiveness optimization perspectives. Moreover their advantages were compared carefully with existed topologies and control techniques. Simulation and experiment results were provided to support the theoretical analysis.
Show less - Date Issued
- 2013
- Identifier
- CFE0005286, ucf:50540
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0005286
- Title
- rf power amplifier and oscillator design for reliability and variability.
- Creator
-
Chen, Shuyu, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Gong, Xun, Wang, Morgan, University of Central Florida
- Abstract / Description
-
CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier...
Show moreCMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable.In this work, a class E power amplifier is designed and laid out using TSMC 0.18 (&)#181;m RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate self-heating effects under different localized heating situations. Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.
Show less - Date Issued
- 2013
- Identifier
- CFE0004664, ucf:49894
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004664
- Title
- High Performance Low Voltage Power MOSFET for High-Frequency Synchronous Buck Converters.
- Creator
-
Yang, Boyi, Shen, Zheng, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Wu, Xinzhang, Xu, Shuming, University of Central Florida
- Abstract / Description
-
Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and...
Show morePower management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications.With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint.It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET.Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35(&)#181;m process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.
Show less - Date Issued
- 2012
- Identifier
- CFE0004642, ucf:49885
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004642
- Title
- On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits.
- Creator
-
Cui, Qiang, Liou, Juin, Yuan, Jiann-Shiun, Wu, Xinzhang, Haralambous, Michael, Shen, Zheng, Deppe, Dennis, University of Central Florida
- Abstract / Description
-
Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD...
Show moreElectrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS.The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT's snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Post-snapback saturation is caused by temperature-induced mobility degradation due to III-V compound semiconductor materials' poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT's InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancement-mode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ((>) 5.2 A It2) under HBM. Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process.In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR's impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter.Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys.
Show less - Date Issued
- 2013
- Identifier
- CFE0004668, ucf:49848
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004668
