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STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY
Title
STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY.
Creator
Liu, Yi, Yuan, Jiann.S., University of Central Florida
Abstract / Description
As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to...
Show moreAs CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide tuning range, and high stability, and a mixer to up-convert or down-convert the signal with good linearity. However, the RF front-end circuit performance is very sensitive to the variation of device parameters. The experimental results show that device performance is degraded significantly subject to HC stress and BD. Therefore, RF front-end performance is degraded by HC and BD effects. With scaling and increasing chip power dissipation, operating temperatures for device have also been increasing. Another reliability concern, which is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias, arises when the operation temperature of devices increases. NBTI has received much attention in recent year and it is found that NIT is present for all stress conditions and NOT is found to occur at high VG. Therefore, the probability of BD in pMOSFET increases with temperature since trapped charges during the NBTI process increase, thus resulting in percolation, a main cause of oxide degradation. The above effects can cause significant degradations in transistors, thus leading to the shifts of RF performance. This dissertation focuses on the following aspects: (1) RF performance degradation in nMOSFET and pMOSFET due to hot carrier and soft breakdown effects are examined experimentally and will be used for circuit application in the future. (2) A modeling method to analyze the gate oxide breakdown effects on RF nMOSFET has been proposed. The device performance drifts due to gate oxide breakdown are examined, breakdown spot resistance and total gate capacitance are extracted before and after stress for 0.16 um CMOS technology. (3) LC voltage controlled oscillator (VCO) performance degradation due to gate oxide breakdown effect is evaluated. (4) NBTI, HCI and BD combined effects on RF performance degradation are investigated. A physical picture illustrating the NBTI induced BD process is presented. A model to evaluate the time-to-failure (TTF) during NBTI is developed. DCIV method is used to extract the densities of NIT and NOT. Measurements show that there is direct correlation between the steplike increase in the gate current and the oxide-trapped charge (NOT). However, Breakdown has nothing to do with interface traps (NIT). (5) It is found that the degradation due to NSH stress is more severe than that of NS stress at high temperature. A model aiming to evaluate the stress-induced degradation is also developed.
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Date Issued
2005
Identifier
CFE0000505, ucf:46465
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000505
HOT CARRIER EFFECT ON LDMOS TRANSISTORS
Title
HOT CARRIER EFFECT ON LDMOS TRANSISTORS.
Creator
Jiang, Liangjun, Yuan, Jiann S., University of Central Florida
Abstract / Description
One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices...
Show moreOne of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.
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Date Issued
2007
Identifier
CFE0001551, ucf:47148
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001551
NEGATIVE BIAS TEMPERATURE INSTABILITY AND CHARGE TRAPPING EFFECTS ON ANALOG AND DIGITAL CIRCUIT RELIABILITY
Title
NEGATIVE BIAS TEMPERATURE INSTABILITY AND CHARGE TRAPPING EFFECTS ON ANALOG AND DIGITAL CIRCUIT RELIABILITY.
Creator
Yu, Yixin, Yuan, Jiann. S., University of Central Florida
Abstract / Description
Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to...
Show moreNanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.
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Date Issued
2007
Identifier
CFE0001930, ucf:47432
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001930
STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY
Title
STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY.
Creator
Yu, Chuanzhao, Yuan, Jiann S., University of Central Florida
Abstract / Description
The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability...
Show moreThe development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
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Date Issued
2006
Identifier
CFE0000948, ucf:46746
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000948
STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES
Title
STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES.
Creator
MA, JUN, Yuan, Jiann S., University of Central Florida
Abstract / Description
In the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused...
Show moreIn the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device – low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device – from device level to circuit level; Studying real voltage stress case – high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.
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Date Issued
2009
Identifier
CFE0002856, ucf:48073
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002856
Energy aware design and analysis for synchronous and asynchronous circuits
Title
Energy aware design and analysis for synchronous and asynchronous circuits.
Creator
Di, Jia, Yuan, Jiann S., Engineering and Computer Science
Abstract / Description
University of Central Florida College of Engineering Thesis; Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale...
Show moreUniversity of Central Florida College of Engineering Thesis; Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale with changing conditions and quality requirements. Scalability is an important figure-of-merit since it allows the end user to implement operational policy just like the user of mobile multimedia equipment needs to select between better quality and longer battery operation time. This dissertation discusses power /energy optimization and performs analysis on both synchronous and asynchronous logic.
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Date Issued
2004
Identifier
CFR0001720, ucf:52913
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFR0001720
THE SIMULATION AND CONTROL OF A GRID-CONNECTED WIND ENERGY CONVERSION SYSTEM
Title
THE SIMULATION AND CONTROL OF A GRID-CONNECTED WIND ENERGY CONVERSION SYSTEM.
Creator
McCartney, Shauna, Yuan, Jiann S., University of Central Florida
Abstract / Description
With the rising cost of petroleum, concerns about exhausting the fossil fuels we depend on for energy, and the subsequent impacts that the burning of these types of fuels have on our environment, countries around the world are paying close attention to the development of renewable types of energy. Consequently, researchers have been trying to develop ways to take advantage of different types of clean and renewable energy sources. Wind energy production, in particular, has been growing at an...
Show moreWith the rising cost of petroleum, concerns about exhausting the fossil fuels we depend on for energy, and the subsequent impacts that the burning of these types of fuels have on our environment, countries around the world are paying close attention to the development of renewable types of energy. Consequently, researchers have been trying to develop ways to take advantage of different types of clean and renewable energy sources. Wind energy production, in particular, has been growing at an increasingly rapid rate, and will continue to do so in the future. In fact, it has become an integral part in supplying our future energy needs, making further advancements in the field exceedingly critical. A 2 MW wind energy conversion system (WECS) is presented and has been simulated via the dynamic simulation software Simulink. This WECS consists of a 2 MW permanent magnet synchronous generator connected to the transmission grid through a power conversion scheme. The topology of this converter system consists of a passive AC/DC rectifier as well as a PWM DC/AC IGBT inverter, used to interface the DC link with the grid. The inverter has an integrated current control system for power factor correction to improve output power stability. The described WECS enhances grid-side tolerance by buffering wind power disturbances demonstrated by its capability to isolate the grid from wind speed fluctuations. It also optimizes wind energy capture through harmonic filtering, enhancing output power quality. These findings have the potential to lead to further advancements including the capability for island operation and integration to a smart grid.
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Date Issued
2010
Identifier
CFE0003484, ucf:48972
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003484
HIGH LINEARITY 5.8 GHZ POWER AMPLIFIER WITH AN INTERNAL LINEARIZER
Title
HIGH LINEARITY 5.8 GHZ POWER AMPLIFIER WITH AN INTERNAL LINEARIZER.
Creator
Wang, Yiheng, Yuan, Jiann S., University of Central Florida
Abstract / Description
A 5.8 GHz RF Power Amplifier (PA) is designed and fabricated in this work, which has very high linearity through a built-in linearizer. The PA is designed, post-layout simulated by Agilent Advanced Design System (ADS) software and fabricated by Win-Semiconductors 0.15µm pHEMT process technology. The post-layout simulation results illustrate the power amplifier can obtained an output power of 23.98 dBm, a power gain of 32.28 dB and a power added efficiency (PAE) of 29% at saturation region,...
Show moreA 5.8 GHz RF Power Amplifier (PA) is designed and fabricated in this work, which has very high linearity through a built-in linearizer. The PA is designed, post-layout simulated by Agilent Advanced Design System (ADS) software and fabricated by Win-Semiconductors 0.15µm pHEMT process technology. The post-layout simulation results illustrate the power amplifier can obtained an output power of 23.98 dBm, a power gain of 32.28 dB and a power added efficiency (PAE) of 29% at saturation region, the 3rd intermodulation distortion (IMD3) of -37.7 dBc at 0 dBm input power is attained when operation frequency is 5.8 GHz. We finally obtain that the output power of 17.97 dBm and power gain of 27.97 dB at input power of -10 dBm, PAE of 11.65% at input power of 0 dBm and the IMD3 of -25.66 dBc at -20 dBm input power by measurement, when operation frequency is 5.2 GHz. So the overall RF performance of the PA demonstrates high power, high efficiency and high linearity.
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Date Issued
2011
Identifier
CFE0003615, ucf:48857
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003615
STUDY OF INGAAS LDMOS FOR POWER CONVERSION APPLICATIONS
Title
STUDY OF INGAAS LDMOS FOR POWER CONVERSION APPLICATIONS.
Creator
Liu, Yidong, Yuan, Jiann S., University of Central Florida
Abstract / Description
In this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-μm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways,...
Show moreIn this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-μm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways, structure with the same cross-sectional dimension, and structure with different thickness of gate dielectric to achieve the same gate capacitance. The on-resistance of the new device shows a big improvement with no degradation on breakdown voltage over traditional device. Also it is indicated from these comparisons that the figure of merit(FOM) Ron·Qg of In0.65Ga0.35As LDMOS shows an average of 91.9% improvement to that of Si LDMOS. To further explore the benefit of using In0.65Ga0.35As LDMOS as switch in power applications, DC-DC buck converter is utilized to observe the performance of LDMOS in terms of power efficiency. The LDMOS performance is experimented with operation frequency of the circuit sweeping in the range from 100 KHz to 100 MHz. It turns out InGaAs LDMOS is good candidate for power applications.
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Date Issued
2009
Identifier
CFE0002686, ucf:48217
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002686