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Title: STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY.
Creator: Liu, Yi, Yuan, Jiann.S., University of Central Florida
Abstract / Description: As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to...
Show moreAs CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide tuning range, and high stability, and a mixer to up-convert or down-convert the signal with good linearity. However, the RF front-end circuit performance is very sensitive to the variation of device parameters. The experimental results show that device performance is degraded significantly subject to HC stress and BD. Therefore, RF front-end performance is degraded by HC and BD effects. With scaling and increasing chip power dissipation, operating temperatures for device have also been increasing. Another reliability concern, which is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias, arises when the operation temperature of devices increases. NBTI has received much attention in recent year and it is found that NIT is present for all stress conditions and NOT is found to occur at high VG. Therefore, the probability of BD in pMOSFET increases with temperature since trapped charges during the NBTI process increase, thus resulting in percolation, a main cause of oxide degradation. The above effects can cause significant degradations in transistors, thus leading to the shifts of RF performance. This dissertation focuses on the following aspects: (1) RF performance degradation in nMOSFET and pMOSFET due to hot carrier and soft breakdown effects are examined experimentally and will be used for circuit application in the future. (2) A modeling method to analyze the gate oxide breakdown effects on RF nMOSFET has been proposed. The device performance drifts due to gate oxide breakdown are examined, breakdown spot resistance and total gate capacitance are extracted before and after stress for 0.16 um CMOS technology. (3) LC voltage controlled oscillator (VCO) performance degradation due to gate oxide breakdown effect is evaluated. (4) NBTI, HCI and BD combined effects on RF performance degradation are investigated. A physical picture illustrating the NBTI induced BD process is presented. A model to evaluate the time-to-failure (TTF) during NBTI is developed. DCIV method is used to extract the densities of NIT and NOT. Measurements show that there is direct correlation between the steplike increase in the gate current and the oxide-trapped charge (NOT). However, Breakdown has nothing to do with interface traps (NIT). (5) It is found that the degradation due to NSH stress is more severe than that of NS stress at high temperature. A model aiming to evaluate the stress-induced degradation is also developed.
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Date Issued: 2005
Identifier: CFE0000505, ucf:46465
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000505

Title: GLOBALLY-ASYNCHRONOUS, LOCALLY-SYNCHRONOUS WRAPPER CONFIGURATIONS FOR POINT-TO-POINT AND MULTI-POINT DATA COMMUNICATION.
Creator: Ravi, Akarsh, Yuan, Jiann, University of Central Florida
Abstract / Description: Globally-Asynchronous, Locally-Synchronous (GALS) design techniques employ the finer points of synchronous and asynchronous design methods to eliminate problems arising due to clock distribution, power dissipation, and large area over head. With the recent rise in the demand for System-on-a-Chip (SoC) designs, global clock distribution and power dissipation due to clock distribution are inevitable. In order to reduce/eliminate the effects of the global clock in synchronous designs and large...
Show moreGlobally-Asynchronous, Locally-Synchronous (GALS) design techniques employ the finer points of synchronous and asynchronous design methods to eliminate problems arising due to clock distribution, power dissipation, and large area over head. With the recent rise in the demand for System-on-a-Chip (SoC) designs, global clock distribution and power dissipation due to clock distribution are inevitable. In order to reduce/eliminate the effects of the global clock in synchronous designs and large area overhead in asynchronous designs, an alternative approach would be to utilize GALS design techniques. Not only do GALS designs eliminate the issue of using a global clock, they also have smaller area overhead when compared to purely asynchronous designs. Among the various GALS design approaches proposed till date, this thesis focuses on the working and implementation of Asynchronous Wrapper designs proposed by Muttersbach et al., in [1, 2]. This thesis specifically addresses different approaches to incorporate the wrappers in VLSI circuits, rather than discussing the efficiency and viability of GALS design techniques over purely synchronous or asynchronous approaches. It has been proven by researchers [3] that GALS design approaches bring down power consumption due to the elimination of the global clock by small amounts, but there is also a drop in performance. Since the goal of this thesis is to introduce the reader to GALS design techniques and not prove their efficiency, it is out of the scope of this thesis to validate the results shown in [3]. In our aim to introduce the reader to GALS design techniques, we first provide a comparison of synchronous and asynchronous design approaches, and then discuss the need for GALS design approaches. We will then address issues affecting GALS such as metastability, latency, flow control, and local clock alteration. After familiarizing the reader with the issues affecting GALS, we will then discuss various GALS design techniques proposed till date. We show the use of asynchronous FIFOs and asynchronous wrappers to realize GALS modules. Two wrapper design approaches are discussed: one being the asynchronous wrapper design proposed by Carlsson et al., in [4], and the other being the asynchronous wrapper design proposed in [1, 2]. An in-depth discussion and analysis of the wrapper design approach proposed in [1, 2] is provided based on the state transition graphs (STGs) that characterize the port-controller AFSMs. Various data transfer channel configurations that incorporate the wrapper port-controllers are designed and realized through VHDL codes, with their functioning verified through simulation results. Design examples showing the working of asynchronous wrappers to achieve point-to-point, synchronous-synchronous and synchronous-asynchronous data communication are provided. Finally, a design example to achieve multi-point data communication is realized. This example incorporates a previously proposed idea. We provide a modification to this idea by designing an arbiter that arbitrates between two separate requests coming into a multi-input port. Through the above design examples, the functionality and working of GALS asynchronous wrappers are verified, and recommendations for modifications are made to achieve flexible multi-point data communication.
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Date Issued: 2004
Identifier: CFE0000238, ucf:46245
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000238

Title: LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS MEMS SENSORS.
Creator: Sadat, Md Anwar, Yuan, Jiann, University of Central Florida
Abstract / Description: A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a...
Show moreA sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.
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Date Issued: 2004
Identifier: CFE0000304, ucf:46318
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000304

Title: HOT CARRIER EFFECT ON LDMOS TRANSISTORS.
Creator: Jiang, Liangjun, Yuan, Jiann S., University of Central Florida
Abstract / Description: One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices...
Show moreOne of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.
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Date Issued: 2007
Identifier: CFE0001551, ucf:47148
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001551

Title: NEGATIVE BIAS TEMPERATURE INSTABILITY AND CHARGE TRAPPING EFFECTS ON ANALOG AND DIGITAL CIRCUIT RELIABILITY.
Creator: Yu, Yixin, Yuan, Jiann. S., University of Central Florida
Abstract / Description: Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to...
Show moreNanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.
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Date Issued: 2007
Identifier: CFE0001930, ucf:47432
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001930

Title: CIRCUIT DESIGN AND RELIABILITY OF A CMOS RECEIVER.
Creator: Yang, Hong, Yuan, Jiann, University of Central Florida
Abstract / Description: This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few...
Show moreThis dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved circuit design methods are proposed, for example, for low noise amplifier (LNA). Except for band filters, local oscillators, and analog-digital converters which are usually implemented by COTS SAW filters and ICs, all the remaining blocks such as switch, LNA, mixer, and local oscillator are designed in MOSIS TSMC 0.35ìm technology in one chip. Meanwhile, this work discusses related circuit reliability issues, which are gaining more and more attention. Breakdown (BD) and hot carrier (HC) effects are important issues in semiconductor industry. Soft-breakdown (SBD) and HC effects on device and RF performance has been reported. Hard-breakdown (HBD) effects on digital circuits have also been investigated. This work uniquely address HBD effects on the RF device and circuit performance, taking low noise amplifier and power amplifier as targets.
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Date Issued: 2004
Identifier: CFE0000212, ucf:46259
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000212

Title: MINIMIZATION OF POWER DISSIPATION IN DIGITAL CIRCUITS USING PIPELINING AND A STUDY OF CLOCK GATING TECHNIQUE.
Creator: Panchangam, Ranganath, Yuan, Jiann, University of Central Florida
Abstract / Description: Power dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been...
Show morePower dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount of power dissipation. The concept of pipelining is explained and the reduction in the power dissipation of the multipliers after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is 0.35µm CMOS and the simulator used is SPECTRE S.
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Date Issued: 2004
Identifier: CFE0000130, ucf:46207
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000130

Title: STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY.
Creator: Yu, Chuanzhao, Yuan, Jiann S., University of Central Florida
Abstract / Description: The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability...
Show moreThe development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
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Date Issued: 2006
Identifier: CFE0000948, ucf:46746
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000948

Title: THE EFFECT OF HOT CARRIER STRESS ON LOW NOISE AMPLIFIER RADIO FREQUENCY PERFORMANCE UNDER WEAK AND STRONG INVERSION.
Creator: Shen, Lin, Yuan, Jiann, University of Central Florida
Abstract / Description: This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the...
Show moreThis thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.
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Date Issued: 2006
Identifier: CFE0000952, ucf:46763
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000952

Title: STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES.
Creator: MA, JUN, Yuan, Jiann S., University of Central Florida
Abstract / Description: In the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused...
Show moreIn the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device – low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device – from device level to circuit level; Studying real voltage stress case – high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.
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Date Issued: 2009
Identifier: CFE0002856, ucf:48073
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002856

Title: Energy aware design and analysis for synchronous and asynchronous circuits.
Creator: Di, Jia, Yuan, Jiann S., Engineering and Computer Science
Abstract / Description: University of Central Florida College of Engineering Thesis; Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale...
Show moreUniversity of Central Florida College of Engineering Thesis; Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale with changing conditions and quality requirements. Scalability is an important figure-of-merit since it allows the end user to implement operational policy just like the user of mobile multimedia equipment needs to select between better quality and longer battery operation time. This dissertation discusses power /energy optimization and performs analysis on both synchronous and asynchronous logic.
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Date Issued: 2004
Identifier: CFR0001720, ucf:52913
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFR0001720

Title: CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT.
Creator: Skaria, Giji, Yuan, Jiann, University of Central Florida
Abstract / Description: This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and...
Show moreThis study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18[micro]m CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
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Date Issued: 2011
Identifier: CFE0004030, ucf:49161
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004030

Title: CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY.
Creator: Kutty, Karan, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were...
Show moreThis study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
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Date Issued: 2010
Identifier: CFE0003360, ucf:48477
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003360

Title: THE SIMULATION AND CONTROL OF A GRID-CONNECTED WIND ENERGY CONVERSION SYSTEM.
Creator: McCartney, Shauna, Yuan, Jiann S., University of Central Florida
Abstract / Description: With the rising cost of petroleum, concerns about exhausting the fossil fuels we depend on for energy, and the subsequent impacts that the burning of these types of fuels have on our environment, countries around the world are paying close attention to the development of renewable types of energy. Consequently, researchers have been trying to develop ways to take advantage of different types of clean and renewable energy sources. Wind energy production, in particular, has been growing at an...
Show moreWith the rising cost of petroleum, concerns about exhausting the fossil fuels we depend on for energy, and the subsequent impacts that the burning of these types of fuels have on our environment, countries around the world are paying close attention to the development of renewable types of energy. Consequently, researchers have been trying to develop ways to take advantage of different types of clean and renewable energy sources. Wind energy production, in particular, has been growing at an increasingly rapid rate, and will continue to do so in the future. In fact, it has become an integral part in supplying our future energy needs, making further advancements in the field exceedingly critical. A 2 MW wind energy conversion system (WECS) is presented and has been simulated via the dynamic simulation software Simulink. This WECS consists of a 2 MW permanent magnet synchronous generator connected to the transmission grid through a power conversion scheme. The topology of this converter system consists of a passive AC/DC rectifier as well as a PWM DC/AC IGBT inverter, used to interface the DC link with the grid. The inverter has an integrated current control system for power factor correction to improve output power stability. The described WECS enhances grid-side tolerance by buffering wind power disturbances demonstrated by its capability to isolate the grid from wind speed fluctuations. It also optimizes wind energy capture through harmonic filtering, enhancing output power quality. These findings have the potential to lead to further advancements including the capability for island operation and integration to a smart grid.
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Date Issued: 2010
Identifier: CFE0003484, ucf:48972
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003484

Title: HIGH LINEARITY 5.8 GHZ POWER AMPLIFIER WITH AN INTERNAL LINEARIZER.
Creator: Wang, Yiheng, Yuan, Jiann S., University of Central Florida
Abstract / Description: A 5.8 GHz RF Power Amplifier (PA) is designed and fabricated in this work, which has very high linearity through a built-in linearizer. The PA is designed, post-layout simulated by Agilent Advanced Design System (ADS) software and fabricated by Win-Semiconductors 0.15µm pHEMT process technology. The post-layout simulation results illustrate the power amplifier can obtained an output power of 23.98 dBm, a power gain of 32.28 dB and a power added efficiency (PAE) of 29% at saturation region,...
Show moreA 5.8 GHz RF Power Amplifier (PA) is designed and fabricated in this work, which has very high linearity through a built-in linearizer. The PA is designed, post-layout simulated by Agilent Advanced Design System (ADS) software and fabricated by Win-Semiconductors 0.15µm pHEMT process technology. The post-layout simulation results illustrate the power amplifier can obtained an output power of 23.98 dBm, a power gain of 32.28 dB and a power added efficiency (PAE) of 29% at saturation region, the 3rd intermodulation distortion (IMD3) of -37.7 dBc at 0 dBm input power is attained when operation frequency is 5.8 GHz. We finally obtain that the output power of 17.97 dBm and power gain of 27.97 dB at input power of -10 dBm, PAE of 11.65% at input power of 0 dBm and the IMD3 of -25.66 dBc at -20 dBm input power by measurement, when operation frequency is 5.2 GHz. So the overall RF performance of the PA demonstrates high power, high efficiency and high linearity.
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Date Issued: 2011
Identifier: CFE0003615, ucf:48857
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003615

Title: STUDY OF ESD EFFECTS ON RF POWER AMPLIFIERS.
Creator: Narasimha Raju, Divya, Yuan, Jiann, University of Central Florida
Abstract / Description: Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even...
Show moreToday, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA's RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.
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Date Issued: 2011
Identifier: CFE0003630, ucf:48881
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003630

Title: CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
Creator: Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
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Date Issued: 2011
Identifier: CFE0003595, ucf:48861
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003595

Title: SOLAR AND FUEL CELL CIRCUIT MODELING, ANALYSIS AND INTEGRATIONS WITH POWER CONVERSION CIRCUITS FOR DISTRIBUTED GENERATION.
Creator: Krishnamurthy, Smitha, Yuan, Jiann, University of Central Florida
Abstract / Description: Renewable energy is considered to be one of the most promising alternatives for the growing energy demand in response to depletion of fossil fuels and undesired global warming issue. With such perspective, Solar Cells and Fuel Cells are most viable, environmentally sound, and sustainable energy sources for power generation. Solar and Fuel cells have created great interests in modern applications including distributed energy generation to provide clean energy. The purpose of this thesis was to...
Show moreRenewable energy is considered to be one of the most promising alternatives for the growing energy demand in response to depletion of fossil fuels and undesired global warming issue. With such perspective, Solar Cells and Fuel Cells are most viable, environmentally sound, and sustainable energy sources for power generation. Solar and Fuel cells have created great interests in modern applications including distributed energy generation to provide clean energy. The purpose of this thesis was to perform a detailed analysis and modeling of Solar and Fuel cells using Cadence SPICE, and to investigate dynamic interactions between the modules and power conversion circuits. Equivalent electronic static and dynamic models for Solar and Fuel Cells, their electrical characteristics, and typical power loss mechanisms associated with them are demonstrated with simulation results. Power conversion circuits for integration with the dynamic models of these renewable low voltage sources are specifically chosen to boost and regulate the input low dc voltage from the modules. The scope of this work was to analyze and model solar and fuel cells to study their terminal characteristics, power loss mechanisms, modules and their dynamics when interfaced with power converters, which would lead to better understanding of these renewable sources in power applications.
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Date Issued: 2009
Identifier: CFE0002815, ucf:48100
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002815

Title: STUDY OF INGAAS LDMOS FOR POWER CONVERSION APPLICATIONS.
Creator: Liu, Yidong, Yuan, Jiann S., University of Central Florida
Abstract / Description: In this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-μm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways,...
Show moreIn this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-μm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways, structure with the same cross-sectional dimension, and structure with different thickness of gate dielectric to achieve the same gate capacitance. The on-resistance of the new device shows a big improvement with no degradation on breakdown voltage over traditional device. Also it is indicated from these comparisons that the figure of merit(FOM) Ron·Qg of In0.65Ga0.35As LDMOS shows an average of 91.9% improvement to that of Si LDMOS. To further explore the benefit of using In0.65Ga0.35As LDMOS as switch in power applications, DC-DC buck converter is utilized to observe the performance of LDMOS in terms of power efficiency. The LDMOS performance is experimented with operation frequency of the circuit sweeping in the range from 100 KHz to 100 MHz. It turns out InGaAs LDMOS is good candidate for power applications.
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Date Issued: 2009
Identifier: CFE0002686, ucf:48217
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002686

Title: CONVENTIONAL AND ZVT SYNCHRONOUS BUCK CONVERTER DESIGN, ANALYSIS, AND MEASUREMENT.
Creator: Cory, Mark, Yuan, Jiann, University of Central Florida
Abstract / Description: The role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, todayÃ‚Â's demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses...
Show moreThe role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, todayÃ‚Â's demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses to a minimum. The power conversion circuitry in a system is a very good place to reduce a large amount of unnecessary loss. This can be done using circuit topologies that are low loss in nature. For low loss and high performance, soft switching topologies have offered solutions in some cases. Also, limited study has been performed on device aging effects on switching mode power converting circuits. The impact of this effect on a converterÃ‚Â's overall efficiency is theoretically known but with little experimental evidence in support. In this thesis, non-isolated buck type switching converters will be the main focus. This type of power conversion is widely used in many systems for DC to DC voltage step down. Newer methods and topologies to raise converter power efficiency are discussed, including a new synchronous ZVT topology . Also, a study has been performed on device aging effects on converter efficiency. Various scenarios of voltage conversion, switching frequency, and circuit components as well as other conditions have been considered. Experimental testing has been performed in both cases, ZVTÃ‚Â's benefits and device aging effects, the results of which are discussed as well.
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Date Issued: 2010
Identifier: CFE0003106, ucf:48650
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003106

CMOS (5)	+ -
ESD (4)	+ -
LDMOS (4)	+ -
RF (4)	+ -
Reliability (4)	+ -

reliability (4)	+ -
2D materials (3)	+ -
TCAD (3)	+ -
power amplifier (3)	+ -
Electrostatic Discharge (2)	+ -
MOSFET (2)	+ -
Mixer (2)	+ -
MoS2 (2)	+ -
NBTI (2)	+ -
PA (2)	+ -
Power MOSFET (2)	+ -
Power Semiconductor (2)	+ -
RF circuit performance (2)	+ -
SCR (2)	+ -
Superjunction (2)	+ -
device reliability (2)	+ -
gate oxide breakdown effect (2)	+ -
hard breakdown (2)	+ -
hot carrier effect (2)	+ -
hot electron (2)	+ -
nanopore (2)	+ -
radio frequency (2)	+ -
soft breakdown (2)	+ -
0.18[micro]m (1)	+ -
28nm CMOS (1)	+ -

University of Central Florida (65)	+ -
Yuan, Jiann-Shiun (48)	+ -
Sundaram, Kalpathy (25)	+ -
Yuan, Jiann (9)	+ -
DeMara, Ronald (8)	+ -

Chow, Lee (7)	+ -
Shen, Zheng (7)	+ -
Yuan, Jiann S. (7)	+ -
Gong, Xun (6)	+ -
Jin, Yier (6)	+ -
Lin, Mingjie (6)	+ -
Liou, Juin (6)	+ -
Wu, Xinzhang (6)	+ -
Abdolvand, Reza (5)	+ -
Kapoor, Vikram (5)	+ -
Roy, Tania (4)	+ -
Chow, Louis (3)	+ -
Salcedo, Javier (3)	+ -
Wei, Lei (3)	+ -
Batarseh, Issa (2)	+ -
Cho, Hyoung Jin (2)	+ -
Fan, Deliang (2)	+ -
Haralambous, Michael (2)	+ -
Khoshavi Najafabadi, Navid (2)	+ -
Liu, Yidong (2)	+ -
Malocha, Donald (2)	+ -
Mikhael, Wasfy (2)	+ -
Prakash, Adithya (2)	+ -
Schulte, Alfons (2)	+ -
Song, Zixia (2)	+ -

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