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- Title
- Multi-transit echo suppression for passive wireless surface acoustic wave sensors using 3rd harmonic unidirectional transducers and Walsh-Hadamard-like reflectors.
- Creator
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Rodriguez Cordoves, Luis, Malocha, Donald, Weeks, Arthur, Abdolvand, Reza, Moharam, Jim, Youngquist, Robert, University of Central Florida
- Abstract / Description
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A passive wireless surface acoustic wave sensor of a delay-line type is composed of an antenna, a transducer that converts the EM signal into a surface acoustic wave, and a set of acoustic reflectors that reflect the incoming signal back out through the antenna. A cavity forms between the transducer and the reflectors, trapping energy and causing multiple unwanted echoes. The work in this dissertation aims to reduce the unwanted echoes so that only the main transit signal is left(-)the signal...
Show moreA passive wireless surface acoustic wave sensor of a delay-line type is composed of an antenna, a transducer that converts the EM signal into a surface acoustic wave, and a set of acoustic reflectors that reflect the incoming signal back out through the antenna. A cavity forms between the transducer and the reflectors, trapping energy and causing multiple unwanted echoes. The work in this dissertation aims to reduce the unwanted echoes so that only the main transit signal is left(-)the signal of interest with sensor information.The contributions of this dissertation include reflective delay-line device response in the form of an infinite impulse response (IIR) filter. This may be used in the future to subtract out unwanted echoes via post-processing. However, this dissertation will use a physical approach to echo suppression by using a unidirectional transducer. Thus a unidirectional transducer is used and also optimized for 3rd harmonic operation. Both the directionality and the coupling of the 3rd harmonic optimized SPUDT are improved over a standard electrode width controlled (EWC) SPUDT. New type of reflectors for the reflective delay-line device are also presented. These use BPSK type coding, similar to that of the Walsh-Hadamard codes. Two types are presented, variable reflectivity and variable chip-lengths. The COM model is used to simulate devices and compare the predicted echo suppression level to that of fabricated devices. Finally, a device is mounted on a tunable antenna and the echo is suppressed on a wireless operating device.
Show less - Date Issued
- 2017
- Identifier
- CFE0006912, ucf:51697
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006912
- Title
- Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
- Creator
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Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
- Abstract / Description
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Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
Show less - Date Issued
- 2015
- Identifier
- CFE0006206, ucf:52889
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006206
