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Triggered Sweep Generators Using Modern Integrated Circuits
Title
Triggered Sweep Generators Using Modern Integrated Circuits.
Creator
Klinger, Arthur Russell, null, null, Engineering
Abstract / Description
Florida Technological University College of Engineering Thesis; The oscilloscope is undoubtedly one of the most important tools in any electronics shop. Presently there are many relatively inexpensive oscilloscopes available, but triggered sweep capability is still reserved for those oscilloscopes costing more than 200 - 500 dollars. The goal of this project was to develop a respectably performing triggered sweep system at a low enough cost to allow inclusion of this valuable feature in any...
Show moreFlorida Technological University College of Engineering Thesis; The oscilloscope is undoubtedly one of the most important tools in any electronics shop. Presently there are many relatively inexpensive oscilloscopes available, but triggered sweep capability is still reserved for those oscilloscopes costing more than 200 - 500 dollars. The goal of this project was to develop a respectably performing triggered sweep system at a low enough cost to allow inclusion of this valuable feature in any oscilloscope. Two of the most important specifications of an oscilloscope are the bandwidth of the vertical amplifier, and the maximum sweep frequency. The broad class of "inexpensive oscilloscope" would include those with a maximum vertical response of 500 KHz to 5 MHz , and a maximum sweep rate of 50 KHz to 500 KHz . Most of these oscilloscopes would not have triggered sweep capability. For about double the cost, the next step upward would be a semi- professional triggered - sweep oscilloscope having a typical vertical response of 1511Hz and a sweep to roughly 2 MHz (500 nsec). Using these classifications as guidelines, a "respectably performing" triggered sweep for inexpensive oscilloscopes may be loosely defined as one having a 500 KHz (2 nsec) sweep, triggerable to at least 5 MHz. Depending on actual cost and application , greater or lesser performance could be considered entirely acceptable. A number of design variations are possible, all of which appear to be a fraction of the cost and complexity of previous designs having comparable specifications . Making this possible are integrated circuits in general, and a modern linear IC "timer" in particular. This report first describes this timer, then uses it as the main element in the generation of a linear ramp. Several trigger and gating circuits are then described. Finally, several of these subcircuits are combined to form three (out of many possible) complete triggered sweep generator systems. As an example of the results, the most expensive circuit costs about 15 dollars in single quantity, yet offers 10 volt per 200 nsec sweep rates, trigger capability from OC to above 15 MHz, trigger level and phase control, and blanking pulse output.
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Date Issued
1973
Identifier
CFR0003511, ucf:53002
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFR0003511
CIRCUIT DESIGN AND RELIABILITY OF A CMOS RECEIVER
Title
CIRCUIT DESIGN AND RELIABILITY OF A CMOS RECEIVER.
Creator
Yang, Hong, Yuan, Jiann, University of Central Florida
Abstract / Description
This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few...
Show moreThis dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved circuit design methods are proposed, for example, for low noise amplifier (LNA). Except for band filters, local oscillators, and analog-digital converters which are usually implemented by COTS SAW filters and ICs, all the remaining blocks such as switch, LNA, mixer, and local oscillator are designed in MOSIS TSMC 0.35ìm technology in one chip. Meanwhile, this work discusses related circuit reliability issues, which are gaining more and more attention. Breakdown (BD) and hot carrier (HC) effects are important issues in semiconductor industry. Soft-breakdown (SBD) and HC effects on device and RF performance has been reported. Hard-breakdown (HBD) effects on digital circuits have also been investigated. This work uniquely address HBD effects on the RF device and circuit performance, taking low noise amplifier and power amplifier as targets.
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Date Issued
2004
Identifier
CFE0000212, ucf:46259
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000212
HOT CARRIER EFFECT ON LDMOS TRANSISTORS
Title
HOT CARRIER EFFECT ON LDMOS TRANSISTORS.
Creator
Jiang, Liangjun, Yuan, Jiann S., University of Central Florida
Abstract / Description
One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices...
Show moreOne of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.
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Date Issued
2007
Identifier
CFE0001551, ucf:47148
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001551
ELECTRO-OPTICAL AND ALL-OPTICAL SWITCHING IN MULTIMODE INTERFERENCE WAVEGUIDES INCORPORATING SEMICONDUCTOR NANOSTRUCTURES
Title
ELECTRO-OPTICAL AND ALL-OPTICAL SWITCHING IN MULTIMODE INTERFERENCE WAVEGUIDES INCORPORATING SEMICONDUCTOR NANOSTRUCTURES.
Creator
Bickel, Nathan, LiKamWa, Patrick, University of Central Florida
Abstract / Description
The application of epitaxially grown, III-V semiconductor-based nanostructures to the development of electro-optical and all-optical switches is investigated through the fabrication and testing of integrated photonic devices designed using multimode interference (MMI) waveguides. The properties and limitations of the materials are explored with respect to the operation of those devices through electrical carrier injection and optical pumping. MMI waveguide geometry was employed as it offered...
Show moreThe application of epitaxially grown, III-V semiconductor-based nanostructures to the development of electro-optical and all-optical switches is investigated through the fabrication and testing of integrated photonic devices designed using multimode interference (MMI) waveguides. The properties and limitations of the materials are explored with respect to the operation of those devices through electrical carrier injection and optical pumping. MMI waveguide geometry was employed as it offered advantages such as a very compact device footprint, low polarization sensitivity, large bandwidth and relaxed fabrication tolerances when compared with conventional single-mode waveguide formats. The first portion of this dissertation focuses on the characterization of the materials and material processing techniques for the monolithic integration of In0.15Ga0.85As/GaAs self-assembled quantum dots (SAQD) and InGaAsP/InGaAsP multiple quantum wells (MQW). Supplemental methods for post-growth bandgap tuning and waveguide formation were developed, including a plasma treatment process which is demonstrated to reliably inhibit thermally induced interdiffusion of Ga and In atoms in In0.15Ga0.85As/GaAs quantum dots. The process is comparable to the existing approach of capping the SAQD wafer with TiO2, while being simpler to implement along-side companion techniques such as impurity free vacancy disordering. Study of plasma-surface interactions in both wafer structures suggests that the effect may be dependent on the composition of the contact layer. The second portion of this work deals with the design, fabrication, and the testing of MMI switches which are used to investigate the limits of electrical current control when employing SAQD as the active core material. A variable power splitter based on a 3-dB MMI coupler is used to analyze the effects of sub-microsecond electrical current pulses in relation to carrier and thermal nonlinearities. Electrical current controlled switching of the variable power splitter and a tunable 2 x 2 MMI coupler is also demonstrated. The third part of this dissertation explores the response of In0.15Ga0.85As/GaAs SAQD waveguide structures to photogenerated carriers. Also presented is a simple, but effective, design modification to the 2 x 2 MMI cross-coupler switch that allows control over the carrier distribution within the MMI waveguide. This technique is combined with selective-area bandgap tuning to demonstrate a compact, working, all-optical MMI based switch.
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Date Issued
2010
Identifier
CFE0003220, ucf:48568
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003220
Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event
Title
Design and Simulation of Device Failure Models for Electrostatic Discharge (ESD) Event.
Creator
Miao, Meng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description
In this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide...
Show moreIn this dissertation, the research mainly focused on discussing ESD failure event simulation and ESD modeling, seeking solutions for ESD issues by simulating ESD event and predict possible ESD reliability problem in IC design. The research involves failure phenomenon caused by ESD/ EOS stress, mainly on the thermal failure due to inevitable self-heating during an ESD stress. Standard Complementary Metal-Oxide-Semiconductor (CMOS) process and high voltage Doublediffusion Metal-Oxide-Semiconductor (DMOS) process are used for design of experiment. A multi-function test platform High Power Pulse Instrument (HPPI) is used for ESD event evaluation and device characterization. SPICE-like software ADICE is for back-end simulation.Electrostatic Discharges (ESD) is one of the hazard that may affect IC circuit function and cause serious damage to the chip. The importance of ESD protection has been raised since the CMOS technology advanced and the dimension of transistors scales down. On the other hand, the variety of applications of chips is also making corresponding ESD protection difficult to meet different design requirement. Aside from typical requirements such as core circuit operation voltage, maximum accepted leakage current, breakdown conditions for the process and overall device sizes, special applications like radio frequency and power electronic requires ESD to be low parasitic capacitance and can sustain high level energy. In that case, a proper ESD protection design demands not only a robust ESD protection scheme, but co-design with the inner circuit. For that purpose, it is necessary to simulate the results of ESD impact on IC and find out possible weak point of the circuit and improve it. The first step of the simulation is to have corresponding models available. Unfortunately, ESD models, especially there are lack of circuit-level ESD models that provide quick and accurate prediction of ESD event.In this dissertation paper, ESD models, especially ESD failure models for device thermal failure are introduced, with modeling methodology accordingly. First, an introduction for ESD event and typical ESD protection schemes are introduced. Its purpose is to give basic concept of ESD. For ESD failure models, two typical types can be categorized depends on the physical mechanisms that cause the ESD damage. One is the gate oxide breakdown, which is electric field related. The other is the thermal-related failure, which stems from the self-heating effect associated with the large current passing through the ESD protection structure. The first one has become increasingly challenging with the aggressive scaling of the gate dielectric in advanced processes and ESD protection for that need to be carefully designed. The second one, thermal failure widely exists in semiconductor devices as long as there is ESD current flow through the device and accumulate heat at junctions. Considering the universality of thermal failure in ESD device, it is imperative to establish a model to simulate ESD caused thermal failure.Several works related to ESD model can be done. One crucial part for a failure model is to define the failure criterion. As common solution for ESD simulation and failure prediction. The maximum current level or breakdown voltage is used to judge whether a device fails under ESD stresses. Such failure criteria based on measurable voltage or current values are straightforward and can be easy to implemented in simulation tools. However, the shortcoming of these failure criteria is each failure criterion is specifically designed for certain ESD stress condition. For example, the failure voltage level for Human Body Model and Charged Device Model are quite different, and it is hard to judge a device's ESD capability under standard test conditions based on its transmission line pulse test result. So it is necessary to look deeper into the physical mechanism of device failure under ESD and find a more universal failure criterion for various stress conditions.As one of the major failure mechanisms, thermal failure evaluated by temperature is a more universal failure criterion for device failure under ESD stress. Whatever the stress model is, the device will fail if a critical temperature is reached at certain part inside the device and cause structural damage. Then finding out that critical temperature is crucial to define the failure point for device thermal failure. One chapter of this dissertation will focus on discussing this issue and propose a simple method to give close estimation of the real failure temperature for typical ESD devices.Combined these related works, a comprehensive diode model for ESD simulation is proposed. Using existing ESD models, diode I-V characteristic from low current turn-on to high current saturation can be simulated. By using temperature as the failure criterion, the last point of diode operation, or the second breakdown point, can be accurately predicted. Additional investigation of ESD capability of devices for special case like vertical GaN diode is discussed in Chapter IV. Due to the distinct material property of GaN, the vertical GaN diode exhibits unique and interesting quasi-static I-V curves quite different from conventional silicon semiconductor devices. And that I-V curve varies with different pulse width, indicating strong conductivity modulation of diode neutral region that will delay the complete turn-on of the vertical GaN diode.
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Date Issued
2017
Identifier
CFE0006626, ucf:51291
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006626
Novel Computational Methods for Integrated Circuit Reverse Engineering
Title
Novel Computational Methods for Integrated Circuit Reverse Engineering.
Creator
Meade, Travis, Zhang, Shaojie, Jin, Yier, Orooji, Ali, Zou, Changchun, Lin, Mingjie, University of Central Florida
Abstract / Description
Production of Integrated Circuits (ICs) has been largely strengthened by globalization. System-on-chip providers are capable of utilizing many different providers which can be responsible for a single task. This horizontal structure drastically improves to time-to-market and reduces manufacturing cost. However, untrust of oversea foundries threatens to dismantle the complex economic model currently in place. Many Intellectual Property (IP) consumers become concerned over what potentially...
Show moreProduction of Integrated Circuits (ICs) has been largely strengthened by globalization. System-on-chip providers are capable of utilizing many different providers which can be responsible for a single task. This horizontal structure drastically improves to time-to-market and reduces manufacturing cost. However, untrust of oversea foundries threatens to dismantle the complex economic model currently in place. Many Intellectual Property (IP) consumers become concerned over what potentially malicious or unspecified logic might reside within their application. This logic which is inserted with the intention of causing harm to a consumer has been referred to as a Hardware Trojan (HT).To help IP consumers, researchers have looked into methods for finding HTs. Such methods tend to rely on high-level information relating to the circuit, which might not be accessible. There is a high possibility that IP is delivered in the gate or layout level. Some services and image processing methods can be leveraged to convert layout level information to gate-level, but such formats are incompatible with detection schemes that require hardware description language.By leveraging standard graph and dynamic programming algorithms a set of tools is developed that can help bridge the gap between gate-level netlist access and HT detection. To help in this endeavor this dissertation focuses on several problems associated with reverse engineering ICs. Logic signal identification is used to find malicious signals, and logic desynthesis is used to extract high level details.Each of the proposed method have their results analyzed for accuracy and runtime. It is found that method for finding logic tends to be the most difficult task, in part due to the degree of heuristic's inaccuracy. With minor improvements moderate sized ICs could have their high-level function recovered within minutes, which would allow for a trained eye or automated methods to more easily detect discrepancies within a circuit's design.
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Date Issued
2017
Identifier
CFE0006896, ucf:51716
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006896
RF Energy Harvesting for Implantable ICs with On-chip Antenna
Title
RF Energy Harvesting for Implantable ICs with On-chip Antenna.
Creator
Liu, Yu-chun, Yuan, Jiann-Shiun, Gong, Xun, Jones, W, University of Central Florida
Abstract / Description
Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite...
Show moreNowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1(&)#215;1(&)#215;2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.
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Date Issued
2014
Identifier
CFE0005202, ucf:50652
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0005202
Adaptive Architectural Strategies for Resilient Energy-Aware Computing
Title
Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
Creator
Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
Abstract / Description
Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
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Date Issued
2015
Identifier
CFE0006206, ucf:52889
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006206