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Title: ARCHITECTURAL SUPPORT FOR IMPROVING SYSTEMHARDWARE/SOFTWARE RELIABILITY.
Creator: Dimitrov, Martin, Zhou, Huiyang, University of Central Florida
Abstract / Description: It is a great challenge to build reliable computer systems with unreliable hardware and buggy software. On one hand, software bugs account for as much as 40% of system failures and incur high cost, an estimate of $59.5B a year, on the US economy. On the other hand, under the current trends of technology scaling, transient faults (also known as soft errors) in the underlying hardware are predicted to grow at least in proportion to the number of devices being integrated, which further...
Show moreIt is a great challenge to build reliable computer systems with unreliable hardware and buggy software. On one hand, software bugs account for as much as 40% of system failures and incur high cost, an estimate of $59.5B a year, on the US economy. On the other hand, under the current trends of technology scaling, transient faults (also known as soft errors) in the underlying hardware are predicted to grow at least in proportion to the number of devices being integrated, which further exacerbates the problem of system reliability. We propose several methods to improve system reliability both in terms of detecting and correcting soft-errors as well as facilitating software debugging. In our first approach, we detect instruction-level anomalies during program execution. The anomalies can be used to detect and repair soft-errors, or can be reported to the programmer to aid software debugging. In our second approach, we improve anomaly detection for software debugging by detecting different types of anomalies as well as by removing false-positives. While the anomalies reported by our first two methods are helpful in debugging single-threaded programs, they do not address concurrency bugs in multi-threaded programs. In our third approach, we propose a new debugging primitive which exposes the non-deterministic behavior of parallel programs and facilitates the debugging process. Our idea is to generate a time-ordered trace of events such as function calls/returns and memory accesses in different threads. In our experience, exposing the time-ordered event information to the programmer is highly beneficial for reasoning about the root causes of concurrency bugs.
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Date Issued: 2010
Identifier: CFE0002975, ucf:47941
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002975

Title: Software quality assurance.
Creator: Soistman, Edward C., null, null, Engineering
Abstract / Description: University of Central Florida College of Engineering Thesis; The problems associated with software development and use are investigated from a management point of view. Having identified the critical aspects of effective software management, an approach is suggested for the creation and implementation of a software quality assurance program, Particular attention is focused on the concept of Life Cycle Procurement as currently utilized by the Department of Defense. The research was...
Show moreUniversity of Central Florida College of Engineering Thesis; The problems associated with software development and use are investigated from a management point of view. Having identified the critical aspects of effective software management, an approach is suggested for the creation and implementation of a software quality assurance program, Particular attention is focused on the concept of Life Cycle Procurement as currently utilized by the Department of Defense. The research was accomplished in two phases. The first consisted of an extensive literature search, seminar attendance and participation in several working groups assigned the responsibility for establishing software quality assurance guidelines. The second phase involved direct participation in the development of a formal software quality assurance program. The report is written in a manner designed to guide a non-technically oriented manager through a complete analysis of software, its measures of quality, its problem sources and the most promising techniques which can he used to control and evaluate its development.
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Date Issued: 1979
Identifier: CFR0003518, ucf:52989
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFR0003518

Title: An Analytical Investigation of Prestressed Beam Bridge Performance Before and After Widening.
Creator: ORiordan Adjah, Chris, Zhou, Lei, Chopra, Manoj, Catbas, Necati, University of Central Florida
Abstract / Description: As traffic and congestion increase, so does the likelihood of collisions. The solution to this problem is usually through a rehabilitation process with two primary options: (1) widening/expansion of existing roadway and bridges and (2) complete replacement (new construction) of roadway and bridges. The first option is the most feasible and cost-effective. While roadway widening/expansion pose minimal issues, the same cannot be said of bridge widening. An existing bridge presents a multitude...
Show moreAs traffic and congestion increase, so does the likelihood of collisions. The solution to this problem is usually through a rehabilitation process with two primary options: (1) widening/expansion of existing roadway and bridges and (2) complete replacement (new construction) of roadway and bridges. The first option is the most feasible and cost-effective. While roadway widening/expansion pose minimal issues, the same cannot be said of bridge widening. An existing bridge presents a multitude of challenges during the planning and design phases, during construction, and throughout the structure's service life. Special attention is required in both the design and detailing of the widening in order to minimize construction and maintenance problems. The primary objective of this dissertation is to present a better understanding of structural behavior and capacity by studying an existing widened structure: a bridge that has been in service for over 40 years (constructed in 1972 and widened in 2002). The load demand on this bridge has doubled over the years. Consequently, the widened structural system is composed of four-span continuous prestressed concrete bridge segments.To better understand the widened 2002 bridge used in this study, an initial comparative analysis was performed, comparing the original 1972 bridge and the 2002 widened bridge. This comparative analysis included a determination of bridge capacity, distribution factors, and load-rating factors using current American Association of State Highway and Transportation Officials (AASHTO) Load and Resistance Factor Design (LRFD) Specifications design codes. However, the original codes used for the two bridges should also be noted, as follows: (1) the AASHTO Load Factor Design (LFD) Code was used for the original bridge; and (2) a combination of the AASHTO LFD and AASHTO LRFD Specifications were used for the existing widened bridge. Linear three-dimensional finite element models were developed for both bridges to obtain the maximum moment and shear values with varying HL-93 load cases for these analyses.To develop models that describe the possible existing condition of the 2002 widened bridge, a nonlinear model of one of the critical members in the structure was developed by changing the most critical parameters. The critical parameters are categorized as material properties and prestress losses. Sensitivity studies were conducted using parametric models for simulations with moving loads for the different load cases using the HL-93 truck. The load-rating and reliability indexes were computed for all the cases under different loading conditions. The parameters that have the most influence on load rating and reliability are also presented in the analyses. The information generated from these analyses can be used for better(-)focused visual inspection and widened bridge load rating criteria, and can also be used for developing a long(-)term widening structural monitoring plan. Additionally, this study will be used as a benchmark for future studies, and to establish a procedure and methodology for future bridge widening projects.
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Date Issued: 2017
Identifier: CFE0006773, ucf:51866
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006773

Title: An approach to improve the failure rate model of a solid state laser by utilizing the Physics of Failure Methodology.
Creator: Thompson, Omar, Kincaid, John, Bass, Michael, Clarke, Thomas, Wiegand, Rudolf, Shumaker, Randall, Bass, Michael, University of Central Florida
Abstract / Description: The ability to predict the failure rate of any military laser is very critical. In-field laser usage does not support the troubleshooting and repairing of a complex electro optical system. The only published laser failure rate model was last updated by the Department of Defense in 1975. Consequently, the failure rate predicted is inaccurate due to model deficiencies. This dissertatiodatn has developed a laser failure rate model for diode pumped lasers with improved failure rate prediction...
Show moreThe ability to predict the failure rate of any military laser is very critical. In-field laser usage does not support the troubleshooting and repairing of a complex electro optical system. The only published laser failure rate model was last updated by the Department of Defense in 1975. Consequently, the failure rate predicted is inaccurate due to model deficiencies. This dissertatiodatn has developed a laser failure rate model for diode pumped lasers with improved failure rate prediction accuracy. The model has surpassed the capabilities of the Department of Defense model by the inclusion of key performance attributes that are currently not taken into account. The scope of work completed was based on a tailored Physics of Failure methodology. The research approach implemented was: 1. Integration of Failure Mode and Effects Analysis to evaluate deployed laser failure. 2. Beam simulation for alignment tolerance analysis. 3. Thermal and vibration effects analysis on laser performance. 4. Analysis and development of a methodology to represent a resonator failure rate model. A secondary contribution of this research effort is supporting the update of the current laser failure rate model. The success of revising the current model relies on leveraging the work of other organizations in the area of failure rate modeling and reliability predictions.
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Date Issued: 2011
Identifier: CFE0004587, ucf:49214
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004587

Title: ACCELERATED LIFE TESTING OF SUBSEA EQUIPMENT UNDER HYDROSTATIC PRESSURE.
Creator: Thiraviam, Amar Raja, Malone, Linda, University of Central Florida
Abstract / Description: Accelerated Life Testing (ALT) is an effective method of demonstrating and improving product reliability in applications where the products are expected to perform for a long period of time. ALT accelerates a given failure mode by testing at amplified stress level(s) in excess of operational limits. Statistical analysis (parameter estimation) is then performed on the data, based on an acceleration model to make life predictions at use level. The acceleration model thus forms the basis of...
Show moreAccelerated Life Testing (ALT) is an effective method of demonstrating and improving product reliability in applications where the products are expected to perform for a long period of time. ALT accelerates a given failure mode by testing at amplified stress level(s) in excess of operational limits. Statistical analysis (parameter estimation) is then performed on the data, based on an acceleration model to make life predictions at use level. The acceleration model thus forms the basis of accelerated life testing methodology. Well established accelerated models such as the Arrhenius model and the Inverse Power Law (IPL) model exist for key stresses such as temperature and voltage. But there are other stresses like subsea pressure, where there is no clear model of choice. This research proposes a pressure-life (acceleration) model for the first time for life prediction under subsea pressure for key mechanical/physical failure mechanisms. Three independent accelerated tests were conducted and their results analyzed to identify the best model for the pressure-life relationship. The testing included material tests in standard coupons to investigate the effect of subsea pressure on key physical, mechanical, and electrical properties. Tests were also conducted at the component level on critical components that function as a pressure barrier. By comparing the likelihood values of multiple reasonable candidate models for the individual tests, the exponential model was identified as a good model for the pressure-life relationship. In addition to consistently providing good fit among the three tests, the exponential model was also consistent with field data (validation with over 10 years of field data) and demonstrated several characteristics that enable robust life predictions in a variety of scenarios. In addition the research also used the process of Bayesian analysis to incorporate prior information from field and test data to bolster the results and increase the confidence in the predictions from the proposed model.
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Date Issued: 2010
Identifier: CFE0003411, ucf:48422
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003411

Title: Research on Improving Reliability, Energy Efficiency and Scalability in Distributed and Parallel File Systems.
Creator: Zhang, Junyao, Wang, Jun, Zhang, Shaojie, Lee, Jooheung, University of Central Florida
Abstract / Description: With the increasing popularity of cloud computing and "Big data" applications, current data centers are often required to manage petabytes or exabytes of data. To store this huge amount of data, thousands or tens of thousands storage nodes are required at a single site. This imposes three major challenges for storage system designers: (1) Reliability---node failure in these datacenters is a normal occurrence rather than a rare situation. This makes data reliability a great concern. (2) Energy...
Show moreWith the increasing popularity of cloud computing and "Big data" applications, current data centers are often required to manage petabytes or exabytes of data. To store this huge amount of data, thousands or tens of thousands storage nodes are required at a single site. This imposes three major challenges for storage system designers: (1) Reliability---node failure in these datacenters is a normal occurrence rather than a rare situation. This makes data reliability a great concern. (2) Energy efficiency---a data center can consume up to 100 times more energy than a standard office building. More than 10% of this energy consumption can be attributed to storage systems. Thus, reducing the energy consumption of the storage system is key to reducing the overall consumption of the data center.(3) Scalability---with the continuously increasing size of data, maintaining the scalability of the storage systems is essential. That is, the expansion of the storage system should be completed efficiently and without limitations on the total number of storage nodes or performance.This thesis proposes three ways to improve the above three key features for current large-scale storage systems. Firstly, we define the problem of "reverse lookup", namely finding the list of objects (blocks) for a failed node. As the first step of failure recovery, this process is directly related to the recovery/reconstruction time. While existing solutions use metadata traversal or data distribution reversing methods for reverse lookup, which are either time consuming or expensive, a deterministic block placement can achieve fast and efficient reverse lookup.However, the deterministic placement solutions are designed for centralized, small-scale storage architectures such as RAID etc.. Due to their lacking of scalability, they cannot be directly applied in large-scale storage systems. In this paper, we propose Group-Shifted Declustering (G-SD), a deterministic data layout for multi-way replication. G-SD addresses the scalability issue of our previous Shifted Declustering layout and supports fast and efficient reverse lookup.Secondly, we define a problem: "how to balance the performance, energy, and recovery in degradation mode for an energy efficient storage system?". While extensive researches have been proposed to tradeoff performance for energy efficiency under normal mode, the system enters degradation mode when node failure occurs, in which node reconstruction is initiated. This very process requires a number of disks to be spun up and requires a substantial amount of I/O bandwidth, which will not only compromise energy efficiency but also performance. Without considering the I/O bandwidth contention between recovery and performance, we find that the current energy proportional solutions cannot answer this question accurately. This thesis present PERP, a mathematical model to minimize the energy consumption for a storage systems with respect to performance and recovery. PERP answers this problem by providing the accurate number of nodes and the assigned recovery bandwidth at each time frame.Thirdly, current distributed file systems such as Google File System(GFS) and Hadoop Distributed File System (HDFS), employ a pseudo-random method for replica distribution and a centralized lookup table (block map) to record all replica locations. This lookup table requires a large amount of memory and consumes a considerable amount of CPU/network resources on the metadata server. With the booming size of "Big Data", the metadata server becomes a scalability and performance bottleneck. While current approaches such as HDFS Federation attempt to "horizontally" extend scalability by allowing multiple metadata servers, we believe a more promising optimization option is to "vertically" scale up each metadata server. We propose Deister, a novel block management scheme that builds on top of a deterministic declustering distribution method Intersected Shifted Declustering (ISD). Thus both replica distribution and location lookup can be achieved without a centralized lookup table.
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Date Issued: 2015
Identifier: CFE0006238, ucf:51082
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006238

Title: The Impact of Automation Reliability and Fatigue on Reliance.
Creator: Wohleber, Ryan, Matthews, Gerald, Reinerman, Lauren, Szalma, James, Funke, Gregory, Jentsch, Florian, University of Central Florida
Abstract / Description: The objective of this research is to inform th(&)#172;(&)#172;e design of dynamic interfaces to optimize unmanned aerial vehicle (UAV) operator reliance on automation. A broad goal of the U.S. military is to improve the ratio of UAV operators to UAVs controlled. Accomplishing this goal requires the use of automation; however, the benefits of automation are jeopardized without appropriate operator reliance. To improve reliance on automation, this effort sought to accomplish several objectives...
Show moreThe objective of this research is to inform th(&)#172;(&)#172;e design of dynamic interfaces to optimize unmanned aerial vehicle (UAV) operator reliance on automation. A broad goal of the U.S. military is to improve the ratio of UAV operators to UAVs controlled. Accomplishing this goal requires the use of automation; however, the benefits of automation are jeopardized without appropriate operator reliance. To improve reliance on automation, this effort sought to accomplish several objectives organized into phases. The first phase aimed to validate metrics that could be used to gauge operator fatigue online, to understand how the reliability of automated systems influences subjective and objective responses, and to understand how the impact of automation reliability changes with different levels of fatigue. To that end, this study employed a multiple UAV simulation containing several tasks. Findings for a challenging Image Analysis task indicated a decrease in accuracy and reliance with time. Both accuracy and reliance were lower with an unreliable automated decision making aid (60% reliability) than with a reliable automated decision making aid (86.7% reliability). Further, a significant interaction indicated that reliance diminished more quickly when the automated aid was less reliable. Concerning the identification of possible eye tracking measures for fatigue, metrics for percentage of eye closure (PERCLOS), blinks, fixations, and dwell time registered changes with time on task. Fixation metrics registered reliability differences. The second phase sought to use outcomes from the first phase to build two algorithms, based on eye tracking, to drive continuous diagnostic monitoring, one simple and another complex. These algorithms were intended to diagnose the passive fatigue state of UAV operators and used subjective task engagement as the dependent variable. The simple algorithm used PERCLOS and total dwell time within the automated tasking area. The complex algorithm added percent of cognitive fixations and frequency of express fixations. The complex algorithm successfully predicted task engagement, primarily on the strength of percentage of cognitive fixations and express fixation frequency metrics.
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Date Issued: 2016
Identifier: CFE0006548, ucf:51323
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006548

Title: HOT CARRIER EFFECT ON LDMOS TRANSISTORS.
Creator: Jiang, Liangjun, Yuan, Jiann S., University of Central Florida
Abstract / Description: One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices...
Show moreOne of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.
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Date Issued: 2007
Identifier: CFE0001551, ucf:47148
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001551

Title: EFFECT OF REPEATED FUNCTION ALLOCATION AND RELIABILITY ON AUTOMATION INDUCED MONITORING INEFFICIENCY.
Creator: Jones, Lauriann, Mouloua, Mustapha, University of Central Florida
Abstract / Description: The purpose of this study is to extend previous findings of Mouloua, Parasuraman, and Molloy (1993), Parasuraman, Mouloua, and Molloy (1996), Hilburn, Parasuraman, and Mouloua (1996), and Oakley, Mouloua, and Hancock (2003) by: 1) examining the effect of repeated adaptive function allocation to manual control of minimal length (5 minutes) to reduce of human error and minimize workload; 2) explore the placement or timing of adaptive function allocation intervals (approximately 20 minutes of...
Show moreThe purpose of this study is to extend previous findings of Mouloua, Parasuraman, and Molloy (1993), Parasuraman, Mouloua, and Molloy (1996), Hilburn, Parasuraman, and Mouloua (1996), and Oakley, Mouloua, and Hancock (2003) by: 1) examining the effect of repeated adaptive function allocation to manual control of minimal length (5 minutes) to reduce of human error and minimize workload; 2) explore the placement or timing of adaptive function allocation intervals (approximately 20 minutes of automation control to reduce the human operators' monitoring decrement between intervals, maintain adaptive recovery performance levels, and improve response times); 3) examine different levels of automation reliability (30%, 60%, and 90% reliable); 4) explore factors that may be manipulated to reduce automation-induced monitoring inefficiency, increase detection of automation malfunctions, improve situation awareness, reduce response/reaction times, and reduce workload in a simulated complex aviation system. The study was a 2 (non-adaptive control vs. adaptive group) x 3 (30%, 60%, and 90% automation reliability condition) x 4 (repeated 25 minute session) mixed factorial design. Fifty-four undergraduate participants' (i.e., 27 participants per group; 9 participants per condition; at least 18 yrs. of age) percentage of detected malfunctions, response times, and subjective workload were gathered from the Multi-Attribute Task Battery and the NASA TLX. Results indicated a significant improvement in detection of malfunctions and response times during adaptive-function allocation to manual control but without adaptive recovery. There was a significant effect for workload found between baseline measures and experimental sessions by group in the first session but not across experimental sessions. Theoretical and practical implications, limitations and future research are discussed.
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Date Issued: 2007
Identifier: CFE0001874, ucf:47387
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001874

Title: HIGH VOLTAGE BIAS TESTING AND DEGRADATION ANALYSIS OF PHOTOVOLTAIC MODULES.
Creator: Hadagali, Vinaykumar, Dhere, Neelkanth, University of Central Florida
Abstract / Description: This thesis mainly focuses on two important aspects of the photovoltaic modules. The first aspect addressed the high voltage bias testing and data and degradation analysis of high voltage biased thin film photovoltaic modules. The second aspect addressed the issues of reliability and durability of crystalline silicon module. Grid-connected photovoltaic systems must withstand high voltage bias in addition to harsh environmental conditions such as intermittent solar irradiance, high humidity,...
Show moreThis thesis mainly focuses on two important aspects of the photovoltaic modules. The first aspect addressed the high voltage bias testing and data and degradation analysis of high voltage biased thin film photovoltaic modules. The second aspect addressed the issues of reliability and durability of crystalline silicon module. Grid-connected photovoltaic systems must withstand high voltage bias in addition to harsh environmental conditions such as intermittent solar irradiance, high humidity, heat and wind. a-Si:H thin-film photovoltaic modules with earlier generation SnO2:F transparent conducting oxide (TCO) on the front glass installed on the FSEC High Voltage Test Bed were monitored since December 2001. The data was collected on a daily basis and analyzed. The leakage currents for some chosen time period were calculated and compared with the measured values. Current-voltage characteristic measurements were carried out to check any reduction in the power. Samples were cored and extracted for analysis from one of the -600 V biased modules. Leakage currents in high-voltage-biased laminates specially prepared with improved SnO2:F TCO are being monitored in the hot and humid climate in Florida. Negatively-biased modules showed clear signs of delamination. The leakage currents in high-voltage biased photovoltaic modules are functions of both temperature and relative humidity. Photovoltaic module leakage conductance was found to be thermally stimulated with a characteristic activation energy that depends on relative humidity. The adhesional strength was lost completely in the damaged area. Leakage current values from support to ground in new, unframed laminates fabricated with improved SnO2:F TCO layer were ~100 times lower under the high voltage bias in hot and humid environment. Information on the failure of field deployed modules must be complemented with why and how the modules fail while considering the issues of reliability and durability of crystalline silicon module. At present, all the failure modes have not been identified and failure mechanisms have not been understood. Experience has shown that as the materials and processes are changed, reliability issues that apparently had been resolved resurface. A multicrystalline silicon photovoltaic module that was manufactured by a non-US company and that had shown >50% performance loss in field-deployment of <2 years in hot and dry climate were studied for degradation analysis in comparison with a mc-Si module that was manufactured by the same company and that performed well after 10 years of field-deployment in hot and humid climate.. I-V measurements were carried out to analyze the reduction in photovoltaic parameters. Solder bond strength in mc-Si photovoltaic modules were measured to understand early degradation of performance. Samples were cored and extracted for further analysis. Adhesional strength between the busline metallization and the silicon cell in a newer generation mc-Si photovoltaic module was found to be considerably lower than that in the earlier vintage module. These results can be useful for early detection and diagnosis of field reliability issues and could assist in establishing correlation between long-term field data and observations and accelerated environmental stress testing. It is suggested that more detailed study should be undertaken using unencapsulated strings of crystalline silicon modules so as to avoid complication due to encapsulant creeping beneath the ribbons.
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Date Issued: 2005
Identifier: CFE0000798, ucf:46563
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000798

Title: STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY.
Creator: Liu, Yi, Yuan, Jiann.S., University of Central Florida
Abstract / Description: As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to...
Show moreAs CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide tuning range, and high stability, and a mixer to up-convert or down-convert the signal with good linearity. However, the RF front-end circuit performance is very sensitive to the variation of device parameters. The experimental results show that device performance is degraded significantly subject to HC stress and BD. Therefore, RF front-end performance is degraded by HC and BD effects. With scaling and increasing chip power dissipation, operating temperatures for device have also been increasing. Another reliability concern, which is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias, arises when the operation temperature of devices increases. NBTI has received much attention in recent year and it is found that NIT is present for all stress conditions and NOT is found to occur at high VG. Therefore, the probability of BD in pMOSFET increases with temperature since trapped charges during the NBTI process increase, thus resulting in percolation, a main cause of oxide degradation. The above effects can cause significant degradations in transistors, thus leading to the shifts of RF performance. This dissertation focuses on the following aspects: (1) RF performance degradation in nMOSFET and pMOSFET due to hot carrier and soft breakdown effects are examined experimentally and will be used for circuit application in the future. (2) A modeling method to analyze the gate oxide breakdown effects on RF nMOSFET has been proposed. The device performance drifts due to gate oxide breakdown are examined, breakdown spot resistance and total gate capacitance are extracted before and after stress for 0.16 um CMOS technology. (3) LC voltage controlled oscillator (VCO) performance degradation due to gate oxide breakdown effect is evaluated. (4) NBTI, HCI and BD combined effects on RF performance degradation are investigated. A physical picture illustrating the NBTI induced BD process is presented. A model to evaluate the time-to-failure (TTF) during NBTI is developed. DCIV method is used to extract the densities of NIT and NOT. Measurements show that there is direct correlation between the steplike increase in the gate current and the oxide-trapped charge (NOT). However, Breakdown has nothing to do with interface traps (NIT). (5) It is found that the degradation due to NSH stress is more severe than that of NS stress at high temperature. A model aiming to evaluate the stress-induced degradation is also developed.
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Date Issued: 2005
Identifier: CFE0000505, ucf:46465
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000505

Title: CIRCUIT DESIGN AND RELIABILITY OF A CMOS RECEIVER.
Creator: Yang, Hong, Yuan, Jiann, University of Central Florida
Abstract / Description: This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few...
Show moreThis dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved circuit design methods are proposed, for example, for low noise amplifier (LNA). Except for band filters, local oscillators, and analog-digital converters which are usually implemented by COTS SAW filters and ICs, all the remaining blocks such as switch, LNA, mixer, and local oscillator are designed in MOSIS TSMC 0.35ìm technology in one chip. Meanwhile, this work discusses related circuit reliability issues, which are gaining more and more attention. Breakdown (BD) and hot carrier (HC) effects are important issues in semiconductor industry. Soft-breakdown (SBD) and HC effects on device and RF performance has been reported. Hard-breakdown (HBD) effects on digital circuits have also been investigated. This work uniquely address HBD effects on the RF device and circuit performance, taking low noise amplifier and power amplifier as targets.
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Date Issued: 2004
Identifier: CFE0000212, ucf:46259
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000212

Title: STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY.
Creator: Yu, Chuanzhao, Yuan, Jiann S., University of Central Florida
Abstract / Description: The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability...
Show moreThe development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
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Date Issued: 2006
Identifier: CFE0000948, ucf:46746
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000948

Title: Developing new power management and High-Reliability Schemes in Data-Intensive Environment.
Creator: Wang, Ruijun, Wang, Jun, Jin, Yier, DeMara, Ronald, Zhang, Shaojie, Ni, Liqiang, University of Central Florida
Abstract / Description: With the increasing popularity of data-intensive applications as well as the large-scale computingand storage systems, current data centers and supercomputers are often dealing with extremelylarge data-sets. To store and process this huge amount of data reliably and energy-efficiently,three major challenges should be taken into consideration for the system designers. Firstly, power conservation(-)Multicore processors or CMPs have become a mainstream in the current processormarket because of...
Show moreWith the increasing popularity of data-intensive applications as well as the large-scale computingand storage systems, current data centers and supercomputers are often dealing with extremelylarge data-sets. To store and process this huge amount of data reliably and energy-efficiently,three major challenges should be taken into consideration for the system designers. Firstly, power conservation(-)Multicore processors or CMPs have become a mainstream in the current processormarket because of the tremendous improvement in transistor density and the advancement in semiconductor technology. However, the increasing number of transistors on a single die or chip reveals a super-linear growth in power consumption [4]. Thus, how to balance system performance andpower-saving is a critical issue which needs to be solved effectively. Secondly, system reliability(-)Reliability is a critical metric in the design and development of replication-based big data storagesystems such as Hadoop File System (HDFS). In the system with thousands machines and storagedevices, even in-frequent failures become likely. In Google File System, the annual disk failurerate is 2:88%,which means you were expected to see 8,760 disk failures in a year. Unfortunately,given an increasing number of node failures, how often a cluster starts losing data when beingscaled out is not well investigated. Thirdly, energy efficiency(-)The fast processing speeds of the current generation of supercomputers provide a great convenience to scientists dealing with extremely large data sets. The next generation of (")exascale(") supercomputers could provide accuratesimulation results for the automobile industry, aerospace industry, and even nuclear fusion reactors for the very first time. However, the energy cost of super-computing is extremely high, with a total electricity bill of 9 million dollars per year. Thus, conserving energy and increasing the energy efficiency of supercomputers has become critical in recent years.This dissertation proposes new solutions to address the above three key challenges for currentlarge-scale storage and computing systems. Firstly, we propose a novel power management scheme called MAR (model-free, adaptive, rule-based) in multiprocessor systems to minimize the CPU power consumption subject to performance constraints. By introducing new I/O wait status, MAR is able to accurately describe the relationship between core frequencies, performance and power consumption. Moreover, we adopt a model-free control method to filter out the I/O wait status from the traditional CPU busy/idle model in order to achieve fast responsiveness to burst situations and take full advantage of power saving. Our extensive experiments on a physical testbed demonstrate that, for SPEC benchmarks and data-intensive (TPC-C) benchmarks, an MAR prototype system achieves 95.8-97.8% accuracy of the ideal power saving strategy calculated offline. Compared with baseline solutions, MAR is able to save 12.3-16.1% more power while maintain a comparable performance loss of about 0.78-1.08%. In addition, more simulation results indicate that our design achieved 3.35-14.2% more power saving efficiency and 4.2-10.7% less performance loss under various CMP configurations as compared with various baseline approaches such as LAST, Relax,PID and MPC.Secondly, we create a new reliability model by incorporating the probability of replica loss toinvestigate the system reliability of multi-way declustering data layouts and analyze their potential parallel recovery possibilities. Our comprehensive simulation results on Matlab and SHARPE show that the shifted declustering data layout outperforms the random declustering layout in a multi-way replication scale-out architecture, in terms of data loss probability and system reliability by upto 63% and 85% respectively. Our study on both 5-year and 10-year system reliability equipped with various recovery bandwidth settings shows that, the shifted declustering layout surpasses the two baseline approaches in both cases by consuming up to 79 % and 87% less recovery bandwidth for copyset, as well as 4.8% and 10.2% less recovery bandwidth for random layout.Thirdly, we develop a power-aware job scheduler by applying a rule based control method and takinginto account real world power and speedup profiles to improve power efficiency while adheringto predetermined power constraints. The intensive simulation results shown that our proposed method is able to achieve the maximum utilization of computing resources as compared to baselinescheduling algorithms while keeping the energy cost under the threshold. Moreover, by introducinga Power Performance Factor (PPF) based on the real world power and speedup profiles, we areable to increase the power efficiency by up to 75%.
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Date Issued: 2016
Identifier: CFE0006704, ucf:51907
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006704

Title: Development of Decision Support System for Active Traffic Management Systems Considering Travel Time Reliability.
Creator: Chung, Whoibin, Abdel-Aty, Mohamed, Eluru, Naveen, Hasan, Samiul, Cai, Qing, Huang, Hsin-Hsiung, University of Central Florida
Abstract / Description: As traffic problems on roadways have been increasing, active traffic management systems (ATM) using proactive traffic management concept have been deployed on freeways and arterials. The ATM aims to integrate and automate various traffic control strategies such as variable speed limits, queue warning, and ramp metering through a decision support system (DSS). Over the past decade, there have been many efforts to integrate freeways and arterials for the efficient operation of roadway networks....
Show moreAs traffic problems on roadways have been increasing, active traffic management systems (ATM) using proactive traffic management concept have been deployed on freeways and arterials. The ATM aims to integrate and automate various traffic control strategies such as variable speed limits, queue warning, and ramp metering through a decision support system (DSS). Over the past decade, there have been many efforts to integrate freeways and arterials for the efficient operation of roadway networks. It has been required that these systems should prove their effectiveness in terms of travel time reliability. Therefore, this study aims to develop a new concept of a decision support system integrating variable speed limits, queue warning, and ramp metering on the basis of travel time reliability of freeways and arterials.Regarding the data preparation, in addition to collecting multiple data sources such as traffic data, crash data and so on, the types of traffic data sources that can be applied for the analysis of travel time reliability were investigated. Although there are many kinds of real-time traffic data from third-party traffic data providers, it was confirmed that these data cannot represent true travel time reliability through the comparative analysis of measures of travel time reliability. Related to weather data, it was proven that nationwide land-based weather stations could be applicable.Since travel time reliability can be measured by using long-term periods for more than six months, it is necessary to develop models to estimate travel time reliability through real-time traffic data and event-related data. Among various matrix to measure travel time reliability, the standard deviation of travel time rate [minute/mile] representing travel time variability was chosen because it can represent travel time variability of both link and network level. Several models were developed to estimate the standard deviation of travel time rate through average travel time rate, the number of lanes, speed limits, and the amount of rainfall.Finally, a DSS using a model predictive control method to integrate multiple traffic control measures was developed and evaluated. As a representative model predictive control, METANET model was chosen, which can include variable speed limit, queue warning, and ramp metering, separately or combined. The developed DSS identified a proper response plan by comparing travel time reliability among multiple combinations of current and new response values of strategies. In the end, it was found that the DSS provided the reduction of travel time and improvement of its reliability for travelers through the recommended response plans.
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Date Issued: 2019
Identifier: CFE0007615, ucf:52542
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007615

Title: INTERRATER RELIABILITY OF PSYCHOMOTOR SKILL ASSESSMENT IN ATHLETIC TRAINING.
Creator: Craddock, Jason, Boote, David, University of Central Florida
Abstract / Description: Assessment in athletic training education is an evolutionary process that is determined by each individual Athletic Training Education Program. The autonomy authorized by national accreditation standards allows academic programs to determine the appropriate assessment practices that facilitate the meeting of student learning outcomes. Even with autonomy, formative and summative techniques are to be employed in both the didactic and clinical arenas of athletic training education programs. The...
Show moreAssessment in athletic training education is an evolutionary process that is determined by each individual Athletic Training Education Program. The autonomy authorized by national accreditation standards allows academic programs to determine the appropriate assessment practices that facilitate the meeting of student learning outcomes. Even with autonomy, formative and summative techniques are to be employed in both the didactic and clinical arenas of athletic training education programs. The major objective of athletic training education is to prepare students for entry-level practice in athletic training. The purpose of this study was to assess interrater reliability of athletic training faculty and approved clinical instructors in their rating of athletic training student performance on four psychomotor skills. A total of 115 individuals participated in this study. Thirty two faculty and 83 approved clinical instructors completed the online survey The results of this study indicate that the overall reliability was high for the entire population as well as the subgroups analyzed. Even though the overall reliability was high, three specific criteria out of a total of 29 criteria had lower reliability scores. These findings may indicate that there may be a high degree of agreement between academic faculty and approved clinical instructors in the rating of athletic training students in their performance of psychomotor skills.
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Date Issued: 2009
Identifier: CFE0002639, ucf:48232
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002639

Title: Predictive modeling for assessing the reliability of bypass diodes in Photovoltaic modules.
Creator: Shiradkar, Narendra, Sundaram, Kalpathy, Schoenfeld, Winston, Atia, George, Abdolvand, Reza, Xanthopoulos, Petros, University of Central Florida
Abstract / Description: Solar Photovoltaics (PV) is one of the most promising renewable energy technologies for mitigating the effect of climate change. Reliability of PV modules directly impacts the Levelized Cost of Energy (LCOE), which is a metric for cost competitiveness of any energy technology. Further reduction in LCOE of PV through assured long term reliability is necessary in order to facilitate widespread use of solar energy without the need for subsidies. This dissertation is focused on frameworks for...
Show moreSolar Photovoltaics (PV) is one of the most promising renewable energy technologies for mitigating the effect of climate change. Reliability of PV modules directly impacts the Levelized Cost of Energy (LCOE), which is a metric for cost competitiveness of any energy technology. Further reduction in LCOE of PV through assured long term reliability is necessary in order to facilitate widespread use of solar energy without the need for subsidies. This dissertation is focused on frameworks for assessing reliability of bypass diodes in PV modules. Bypass diodes are critical components in PV modules that provide protection against shading. Failure of bypass diode in short circuit results in reducing the PV module power by one third, while diode failure in open circuit leaves the module susceptible for extreme hotspot heating and potentially fire hazard. PV modules, along with the bypass diodes are expected to last at least 25 years in field. The various failure mechanisms in bypass diodes such as thermal runaway, high temperature forward bias operation and thermal cycling are discussed. Operation of bypass diode under shading is modeled and method for calculating the module I-V curve under any shading scenario is presented. Frameworks for estimating the diode temperature in field deployed modules based on Typical Meteorological Year (TMY) data are developed. Model for predicting the susceptibility of bypass diodes for thermal runaway is presented. Diode wear out due to High Temperature Forward Bias (HTFB) operation and Thermal Cycling (TC) is studied under custom designed accelerated tests. Overall, this dissertation is an effort towards estimating the lifetime of bypass diodes in field deployed modules, and therefore, reducing the uncertainty in long term reliability of PV modules.
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Date Issued: 2015
Identifier: CFE0006001, ucf:51023
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006001

Title: FORMALIZATION OF INPUT AND OUTPUT IN MODERN OPERATING SYSTEMS: THE HADLEY MODEL.
Creator: Gerber, Matthew, Leeson, John, University of Central Florida
Abstract / Description: We present the Hadley model, a formal descriptive model of input and output for modern computer operating systems. Our model is intentionally inspired by the Open Systems Interconnection model of networking; I/O as a process is defined as a set of translations between a set of computer-sensible forms, or layers, of information. To illustrate an initial application domain, we discuss the utility of the Hadley model and a potential associated I/O system as a tool for digital forensic...
Show moreWe present the Hadley model, a formal descriptive model of input and output for modern computer operating systems. Our model is intentionally inspired by the Open Systems Interconnection model of networking; I/O as a process is defined as a set of translations between a set of computer-sensible forms, or layers, of information. To illustrate an initial application domain, we discuss the utility of the Hadley model and a potential associated I/O system as a tool for digital forensic investigators. To illustrate practical uses of the Hadley model we present the Hadley Specification Language, an essentially functional language designed to allow the translations that comprise I/O to be written in a concise format allowing for relatively easy verifiability. To further illustrate the utility of the language we present a read/write Microsoft DOS FAT12 and read-only Linux ext2 file system specification written in the new format. We prove the correctness of the read-only side of these descriptions. We present test results from operation of our HSL-driven system both in user mode on stored disk images and as part of a Linux kernel module allowing file systems to be read. We conclude by discussing future directions for the research.
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Date Issued: 2005
Identifier: CFE0000392, ucf:46339
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000392

Title: LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS MEMS SENSORS.
Creator: Sadat, Md Anwar, Yuan, Jiann, University of Central Florida
Abstract / Description: A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a...
Show moreA sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.
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Date Issued: 2004
Identifier: CFE0000304, ucf:46318
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000304

Title: MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT.
Creator: CUI, ZHI, Liou, Juin J., University of Central Florida
Abstract / Description: Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0...
Show moreLong-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
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Date Issued: 2005
Identifier: CFE0000476, ucf:46360
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000476

Reliability (18)	+ -
reliability (14)	+ -
CMOS (3)	+ -
RF (3)	+ -
automation (3)	+ -

Load Rating (2)	+ -
Modeling (2)	+ -
RF circuit performance (2)	+ -
Simulation (2)	+ -
Uncertainty (2)	+ -
device reliability (2)	+ -
gate oxide breakdown effect (2)	+ -
hard breakdown (2)	+ -
hot electron (2)	+ -
performance (2)	+ -
power amplifier (2)	+ -
soft breakdown (2)	+ -
stress (2)	+ -
teacher evaluation (2)	+ -
0.18[micro]m (1)	+ -
000 rpm (1)	+ -
1 inch diameter (1)	+ -
2 inch diameter (1)	+ -
20 (1)	+ -
350 Hz (1)	+ -
ANSYS (1)	+ -
ARMA (1)	+ -
Accelerated Life Testing (1)	+ -
Accelerated Test (1)	+ -
Acceleration Model (1)	+ -

ETD Collection (48)	+ -
Honors Collection (2)	+ -

University of Central Florida (49)	+ -
DeMara, Ronald (7)	+ -
Yuan, Jiann-Shiun (7)	+ -
Sundaram, Kalpathy (5)	+ -
Abdel-Aty, Mohamed (3)	+ -

Lin, Mingjie (3)	+ -
Wang, Jun (3)	+ -
Yuan, Jiann (3)	+ -
Yuan, Jiann S. (3)	+ -
Chopra, Manoj (2)	+ -
Chow, Lee (2)	+ -
Eluru, Naveen (2)	+ -
Jentsch, Florian (2)	+ -
Karwowski, Waldemar (2)	+ -
Liou, Juin J. (2)	+ -
Malone, Linda (2)	+ -
Mouloua, Mustapha (2)	+ -
Shen, Zheng (2)	+ -
Shumaker, Randall (2)	+ -
Song, Zixia (2)	+ -
Szalma, James (2)	+ -
Xanthopoulos, Petros (2)	+ -
Zhang, Shaojie (2)	+ -
Abdolvand, Reza (1)	+ -
Al-Deek, Haitham (1)	+ -
Alexander, Tiffaney (1)	+ -
Alghareb, Faris (1)	+ -
Anderson, Carlos (1)	+ -
Ashraf, Rizwan (1)	+ -
Atia, George (1)	+ -

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