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- Title
- DESIGN, CHARACTERIZATION AND COMPACT MODELING OF NOVEL SILICON CONTROLLED RECTIFIER (SCR)-BASED DEVICES FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPLICATIONS IN INTEGRATED CIRCUITS.
- Creator
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Lou, Lifang, Liou, Juin J., University of Central Florida
- Abstract / Description
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Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have...
Show moreElectrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.
Show less - Date Issued
- 2008
- Identifier
- CFE0002374, ucf:47788
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002374
- Title
- IMPROVING AIRLINE SCHEDULE RELIABILITY USING A STRATEGIC MULTI-OBJECTIVE RUNWAY SLOT ASSIGNMENT SEARCH HEURISTIC.
- Creator
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Hafner, Florian, Sepulveda, Alejandro, University of Central Florida
- Abstract / Description
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Improving the predictability of airline schedules in the National Airspace System (NAS) has been a constant endeavor, particularly as system delays grow with ever-increasing demand. Airline schedules need to be resistant to perturbations in the system including Ground Delay Programs (GDPs) and inclement weather. The strategic search heuristic proposed in this dissertation significantly improves airline schedule reliability by assigning airport departure and arrival slots to each flight in the...
Show moreImproving the predictability of airline schedules in the National Airspace System (NAS) has been a constant endeavor, particularly as system delays grow with ever-increasing demand. Airline schedules need to be resistant to perturbations in the system including Ground Delay Programs (GDPs) and inclement weather. The strategic search heuristic proposed in this dissertation significantly improves airline schedule reliability by assigning airport departure and arrival slots to each flight in the schedule across a network of airports. This is performed using a multi-objective optimization approach that is primarily based on historical flight and taxi times but also includes certain airline, airport, and FAA priorities. The intent of this algorithm is to produce a more reliable, robust schedule that operates in today's environment as well as tomorrow's 4-Dimensional Trajectory Controlled system as described the FAA's Next Generation ATM system (NextGen). This novel airline schedule optimization approach is implemented using a multi-objective evolutionary algorithm which is capable of incorporating limited airport capacities. The core of the fitness function is an extensive database of historic operating times for flight and ground operations collected over a two year period based on ASDI and BTS data. Empirical distributions based on this data reflect the probability that flights encounter various flight and taxi times. The fitness function also adds the ability to define priorities for certain flights based on aircraft size, flight time, and airline usage. The algorithm is applied to airline schedules for two primary US airports: Chicago O'Hare and Atlanta Hartsfield-Jackson. The effects of this multi-objective schedule optimization are evaluated in a variety of scenarios including periods of high, medium, and low demand. The schedules generated by the optimization algorithm were evaluated using a simple queuing simulation model implemented in AnyLogic. The scenarios were simulated in AnyLogic using two basic setups: (1) using modes of flight and taxi times that reflect highly predictable 4-Dimensional Trajectory Control operations and (2) using full distributions of flight and taxi times reflecting current day operations. The simulation analysis showed significant improvements in reliability as measured by the mean square difference (MSD) of filed versus simulated flight arrival and departure times. Arrivals showed the most consistent improvements of up to 80% in on-time performance (OTP). Departures showed reduced overall improvements, particularly when the optimization was performed without the consideration of airport capacity. The 4-Dimensional Trajectory Control environment more than doubled the on-time performance of departures over the current day, more chaotic scenarios. This research shows that airline schedule reliability can be significantly improved over a network of airports using historical flight and taxi time data. It also provides for a mechanism to prioritize flights based on various airline, airport, and ATC goals. The algorithm is shown to work in today's environment as well as tomorrow's NextGen 4-Dimensional Trajectory Control setup.
Show less - Date Issued
- 2008
- Identifier
- CFE0002067, ucf:47572
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002067
- Title
- DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
- Creator
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SALCEDO, Javier, Liou, Juin, University of Central Florida
- Abstract / Description
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The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
Show less - Date Issued
- 2006
- Identifier
- CFE0001213, ucf:46942
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001213
