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STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY
Title
STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY.
Creator
Yu, Chuanzhao, Yuan, Jiann S., University of Central Florida
Abstract / Description
The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability...
Show moreThe development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
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Date Issued
2006
Identifier
CFE0000948, ucf:46746
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000948
LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS MEMS SENSORS
Title
LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS MEMS SENSORS.
Creator
Sadat, Md Anwar, Yuan, Jiann, University of Central Florida
Abstract / Description
A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a...
Show moreA sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.
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Date Issued
2004
Identifier
CFE0000304, ucf:46318
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000304
"Design and Simulation of CMOS RF Active Mixers"
Title
"Design and Simulation of CMOS RF Active Mixers".
Creator
Gibson, Allen, Yuan, Jiann-Shiun, Wei, Lei, Sundaram, Kalpathy, University of Central Florida
Abstract / Description
This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage...
Show moreThis paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 (&)#181;m CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.
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Date Issued
2011
Identifier
CFE0004112, ucf:49086
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0004112
design, characterization and analysis of component level electrostatic discharge (esd) protection solutions
Title
design, characterization and analysis of component level electrostatic discharge (esd) protection solutions.
Creator
Luo, Sirui, Liou, Juin, Yuan, Jiann-Shiun, Gong, Xun, Jin, Yier, Salcedo, Javier, University of Central Florida
Abstract / Description
Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology...
Show moreElectrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level.Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC's pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products.Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to (&)#177; 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR.Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology.ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices' performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range.
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Date Issued
2015
Identifier
CFE0005655, ucf:50189
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0005655
RF Energy Harvesting for Implantable ICs with On-chip Antenna
Title
RF Energy Harvesting for Implantable ICs with On-chip Antenna.
Creator
Liu, Yu-chun, Yuan, Jiann-Shiun, Gong, Xun, Jones, W, University of Central Florida
Abstract / Description
Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite...
Show moreNowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1(&)#215;1(&)#215;2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.
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Date Issued
2014
Identifier
CFE0005202, ucf:50652
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0005202
Reactive Rejuvenation of CMOS Logic Paths using Self-activating Voltage Domains
Title
Reactive Rejuvenation of CMOS Logic Paths using Self-activating Voltage Domains.
Creator
Khoshavi Najafabadi, Navid, DeMara, Ronald, Yuan, Jiann-Shiun, Song, Zixia, University of Central Florida
Abstract / Description
Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to...
Show moreAggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping. Results indicate the effectiveness of power-gating on NBTI/PBTI phenomena and propose a preferred sleep transistor configuration for maximizing higher recovery. Furthermore, the aging effect can manifest itself as timing error on critical speed-paths of the circuit, if a large design guardband is not reserved. To mitigate circuit from BTI-induced aging, the Reactive Rejuvenation (RR) architectural approach is proposed which entails detection and recovery phases. The BTI impact on the critical and near critical paths performance is continuously examined through a lightweight logic circuit which asserts an error signal in the case of any timing violation in those paths. By observing the timing violation occurrence in the system, the timing-sensitive portion of the circuit is recovered from BTI through switching computations to redundant aging-critical voltage domain. The proposed technique achieves aging mitigation and reduced energy consumption as compared to a baseline circuit. Thus, signi?cant voltage guardbands to meet the desired timing speci?cation are avoided result in energy savings during circuit operation.
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Date Issued
2016
Identifier
CFE0006339, ucf:51561
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006339
CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT
Title
CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT.
Creator
Skaria, Giji, Yuan, Jiann, University of Central Florida
Abstract / Description
This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and...
Show moreThis study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18[micro]m CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
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Date Issued
2011
Identifier
CFE0004030, ucf:49161
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0004030
Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories
Title
Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories.
Creator
Salehi Mobarakeh, Soheil, DeMara, Ronald, Fan, Deliang, Turgut, Damla, University of Central Florida
Abstract / Description
The continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation....
Show moreThe continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time.
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Date Issued
2016
Identifier
CFE0006493, ucf:51400
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006493
CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION
Title
CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
Creator
Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description
The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
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Date Issued
2011
Identifier
CFE0003595, ucf:48861
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003595
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES
Title
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
Creator
SALCEDO, Javier, Liou, Juin, University of Central Florida
Abstract / Description
The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
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Date Issued
2006
Identifier
CFE0001213, ucf:46942
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001213