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DESIGN OF A WIDEBAND DUAL-POLARIZED CAVITY BACKED SLOT ANTENNA
Title
DESIGN OF A WIDEBAND DUAL-POLARIZED CAVITY BACKED SLOT ANTENNA.
Creator
Paryani, Rajesh, Wahid, Parveen F, University of Central Florida
Abstract / Description
A new technique for designing wideband dual-polarized cavity-backed slot antennas is presented. The structure is in the form of a double-resonant, dual-polarized slot antenna backed by a shallow substrate integrated cavity with a depth of approximately one tenth the free space wavelength. The presence of the cavity behind the slot enhances the antennaÂÂ's directivity and reduces the possibility of surface wave propagation in the antenna substrate when the element is...
Show moreA new technique for designing wideband dual-polarized cavity-backed slot antennas is presented. The structure is in the form of a double-resonant, dual-polarized slot antenna backed by a shallow substrate integrated cavity with a depth of approximately one tenth the free space wavelength. The presence of the cavity behind the slot enhances the antennaÂÂ's directivity and reduces the possibility of surface wave propagation in the antenna substrate when the element is used in an array environment. Moreover, the dual-polarized nature of this radiating element may be exploited to synthesize any desired polarization (vertical, horizontal, RHCP, or LHCP). The double-resonant behavior observed in this substrate-integrated cavity-backed slot antenna (SICBSA) is utilized to enhance its bandwidth compared to a typical cavity-backed slot antenna. A prototype of the proposed antenna is fabricated and tested. Measurement results indicate that a bandwidth of 19%, an average gain of 5.3 dB, and a wideband differential isolation of 30 dB can be achieved using this technique. The principles of operation along with the measurement results of the fabricated prototype are presented and discussed in this dissertation. The SICBSA is investigated as a candidate for use as an array element. A uniform two element phased array is demonstrated to locate the main beam from boresight to thirty degrees. The potential effects of mutual coupling and surface wave propagation are considered and analyzed.
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Date Issued
2010
Identifier
CFE0003066, ucf:48295
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003066
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES
Title
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
Creator
SALCEDO, Javier, Liou, Juin, University of Central Florida
Abstract / Description
The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
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Date Issued
2006
Identifier
CFE0001213, ucf:46942
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001213