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- Title
- EMBEDDED MAGNETICS FOR POWER SYSTEM ON CHIP (PSOC).
- Creator
-
Lu, Jian, Shen, Z. John, University of Central Florida
- Abstract / Description
-
A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor...
Show moreA novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor concept. Transformer parameters including self- and mutual inductance, and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SoC manufacturing processes with minimal changes to the layout, and open enormous possibilities for realizing cost-effective, high current, high efficiency PSoC's or PSiP's. The design guidelines for single bondwire inductors as well as multi-turn inductors are discussed step by step in several chapters. Not only is the innovated concept for bondwire inductor with ferrite ink presented, but also the practical implementation and design rules are given. With all the well defined steps, people who want to use these bondwire inductors with ferrite ink in their PSoC research or products will find it as simple as using commercial inductors. Last but not least, the PSoC concept using a bondwire inductor is demonstrated by building the prototype of dc-dc buck converter IC as well as the whole package. IC and the whole function block are tested and presented in this work.
Show less - Date Issued
- 2009
- Identifier
- CFE0002952, ucf:47953
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002952
- Title
- DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
- Creator
-
SALCEDO, Javier, Liou, Juin, University of Central Florida
- Abstract / Description
-
The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
Show less - Date Issued
- 2006
- Identifier
- CFE0001213, ucf:46942
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001213
