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- Title
- Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies.
- Creator
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Dong, Aihua, Sundaram, Kalpathy, Fan, Deliang, Gong, Xun, Wei, Lei, Salcedo, Javier, University of Central Florida
- Abstract / Description
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Electrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to...
Show moreElectrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to FinFET technology requires more robust ESD protection however the large parasitic capacitance of ESD protection cell is problematic in high-speed interface design. To reduce the parasitic capacitance, a dual diode silicon controlled rectifier (DD-SCR) is presented in this dissertation. This design can exhibit good trade-offs between ESD robustness and parasitic capacitance characteristics. Besides, different bounding materials lead to performance variations in DD-SCRs are compared. Radio frequency (RF) technology is also demanded low capacitance ESD protection. To address this concern, a ?-network is presented, providing robust ESD protection for 10-60 GHz RF circuit. Like a low pass ? filter, the network can reflect high frequency RF signals and transmit low frequency ESD pulses. Given proper inductor value, networks can work as robust ESD solutions at a certain Giga Hertz frequency range, making this design suitable for broad band protection in RF input/outputs (I/Os). To increase the holding voltage and reduce snapback, a resistor assist triggering heterogeneous stacking structure is presented in this dissertation, which can increase the holding voltage and also keep the trigger voltage nearly as same as a single SCR device.
Show less - Date Issued
- 2018
- Identifier
- CFE0007172, ucf:52251
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007172
- Title
- Transient Safe Operating Area (TSOA) for ESD applications.
- Creator
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Malobabic, Slavica, Liou, Juin, Shen, Zheng, Yuan, Jiann-Shiun, Vinson, James, University of Central Florida
- Abstract / Description
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A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD).A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins.The methodology for input pins includes...
Show moreA methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD).A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins.The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs.The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identified.
Show less - Date Issued
- 2012
- Identifier
- CFE0004405, ucf:49363
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004405
- Title
- Design and Characterization of High Temperature Packaging for Wide-Bandgap Semiconductor Devices.
- Creator
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Grummel, Brian, Shen, Zheng, Sundaram, Kalpathy, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor...
Show moreAdvances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au(-)In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au(-)In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermo-mechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.
Show less - Date Issued
- 2012
- Identifier
- CFE0004499, ucf:49276
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004499
- Title
- DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
- Creator
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SALCEDO, Javier, Liou, Juin, University of Central Florida
- Abstract / Description
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The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
Show less - Date Issued
- 2006
- Identifier
- CFE0001213, ucf:46942
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001213