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THE USE OF FILTERS IN TOPOLOGY
Title
THE USE OF FILTERS IN TOPOLOGY.
Creator
Dasser, Abdellatif, Richardson, Gary, University of Central Florida
Abstract / Description
Sequences are sufficient to describe topological properties in metric spaces or, more generally, topological spaces having a countable base for the topology. However, filters or nets are needed in more abstract spaces. Nets are more natural extension of sequences but are generally less friendly to work with since quite often two nets have distinct directed sets for domains. Operations involving filters are set theoretic and generally certain to filters on the same set. The concept of a filter...
Show moreSequences are sufficient to describe topological properties in metric spaces or, more generally, topological spaces having a countable base for the topology. However, filters or nets are needed in more abstract spaces. Nets are more natural extension of sequences but are generally less friendly to work with since quite often two nets have distinct directed sets for domains. Operations involving filters are set theoretic and generally certain to filters on the same set. The concept of a filter was introduced by H. Cartan in 1937 and an excellent treatment of the subject can be found in N. Bourbaki (1940).
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Date Issued
2004
Identifier
CFE0000202, ucf:46271
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000202
ON-CHIP SPIRAL INDUCTOR/TRANSFORMER DESIGN AND MODELING FOR RF APPLICATIONS
Title
ON-CHIP SPIRAL INDUCTOR/TRANSFORMER DESIGN AND MODELING FOR RF APPLICATIONS.
Creator
Chen, Ji, Liou, Juin, University of Central Florida
Abstract / Description
Passive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) IC's such as low-noise amplifiers and oscillators. High performance inductor has become one of the critical components for voltage controlled oscillator (VCO) design, for its quality factor (Q) value directly affects the VCO phase noise. The optimization of inductor layout can improve its performance, but the...
Show morePassive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) IC's such as low-noise amplifiers and oscillators. High performance inductor has become one of the critical components for voltage controlled oscillator (VCO) design, for its quality factor (Q) value directly affects the VCO phase noise. The optimization of inductor layout can improve its performance, but the improvement is limited by selected technology. Inductor performance is bounded by the thin routing metal and small distance from lossy substrate. On the other hand, the in-accurate inductor modeling further limits the optimization process. The on-chip inductor has been an important research topic since it was first proposed in early 1990's. Significant amount of study has been accomplished and reported in literature; whereas some methods have been used in industry, but not released to public. It is of no doubt that a comprehensive solution is not exist yet. A comprehensive study of previous will be first address. Later author will point out the in-adequacy of skin effect and proximity effect as cause of current crowding in the inductor metal. A model method embedded with new explanation of current crowding is proposed and its applicability in differential inductor and balun is validated. This study leads to a robust optimization routine to improve inductor performance without any addition technology cost and development.
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Date Issued
2006
Identifier
CFE0001364, ucf:46962
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001364
Interval Edge-Colorings of Graphs
Title
Interval Edge-Colorings of Graphs.
Creator
Foster, Austin, Song, Zixia, Reid, Michael, Brennan, Joseph, University of Central Florida
Abstract / Description
A proper edge-coloring of a graph G by positive integers is called an interval edge-coloring if the colors assigned to the edges incident to any vertex in G are consecutive (i.e., those colors form an interval of integers). The notion of interval edge-colorings was first introduced by Asratian and Kamalian in 1987, motivated by the problem of finding compact school timetables. In 1992, Hansen described another scenario using interval edge-colorings to schedule parent-teacher conferences so...
Show moreA proper edge-coloring of a graph G by positive integers is called an interval edge-coloring if the colors assigned to the edges incident to any vertex in G are consecutive (i.e., those colors form an interval of integers). The notion of interval edge-colorings was first introduced by Asratian and Kamalian in 1987, motivated by the problem of finding compact school timetables. In 1992, Hansen described another scenario using interval edge-colorings to schedule parent-teacher conferences so that every person's conferences occur in consecutive slots. A solution exists if and only if the bipartite graph with vertices for parents and teachers, and edges for the required meetings, has an interval edge-coloring.A well-known result of Vizing states that for any simple graph $G$, $\chi'(G) \leq \Delta(G) + 1$, where $\chi'(G)$ and $\Delta(G)$ denote the edge-chromatic number and maximum degree of $G$, respectively. A graph $G$ is called class 1 if $\chi'(G) = \Delta(G)$, and class 2 if $\chi'(G) = \Delta(G) + 1$. One can see that any graph admitting an interval edge-coloring must be of class 1, and thus every graph of class 2 does not have such a coloring.Finding an interval edge-coloring of a given graph is hard. In fact, it has been shown that determining whether a bipartite graph has an interval edge-coloring is NP-complete. In this thesis, we survey known results on interval edge-colorings of graphs, with a focus on the progress of $(a, b)$-biregular bipartite graphs. Discussion of related topics and future work is included at the end. We also give a new proof of Theorem 3.15 on the existence of proper path factors of $(3, 4)$-biregular graphs. Finally, we obtain a new result, Theorem 3.18, which states that if a proper path factor of any $(3, 4)$-biregular graph has no path of length 8, then it contains paths of length 6 only. The new result we obtained and the method we developed in the proof of Theorem 3.15 might be helpful in attacking the open problems mentioned in the Future Work section of Chapter 5.
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Date Issued
2016
Identifier
CFE0006301, ucf:51609
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006301
EFFECTS OF THE SOIL PROPERTIES ON THE MAXIMUM DRY DENSITY OBTAINED FROM THE STANDARD PROCTOR TEST.
Title
EFFECTS OF THE SOIL PROPERTIES ON THE MAXIMUM DRY DENSITY OBTAINED FROM THE STANDARD PROCTOR TEST.
Creator
Arvelo, Andres, Kuo, Shiou-san, University of Central Florida
Abstract / Description
In the construction of highways, airports, and other structures, the compaction of soils is needed to improve its strength. In 1933 Proctor developed a laboratory compaction test to determine the maximum dry density of compacted soils, which can be used for specifications of field compaction. The Compaction of soils is influenced by many factors, the most common are the moisture content, the soil type and the applied compaction energy. The objective of this research is the analysis of the...
Show moreIn the construction of highways, airports, and other structures, the compaction of soils is needed to improve its strength. In 1933 Proctor developed a laboratory compaction test to determine the maximum dry density of compacted soils, which can be used for specifications of field compaction. The Compaction of soils is influenced by many factors, the most common are the moisture content, the soil type and the applied compaction energy. The objective of this research is the analysis of the maximum dry density values based on the soil classification and characterization. The method of choice in the determination of the maximum dry density from different soils was the Standard Proctor Test following the procedure for the standard Proctor test as is explained in ASTM Test Designation D-698. From this investigation, the maximum dry density of eight types of sands was obtained, the sands were classified by using the Unified Soil Classification System. The influence on the maximum dry density of the type of sands, type of fines, amount of fines and distribution of the grain size was determined, followed by a sensitivity analysis that measured the influence of these parameters on the obtained maximum dry density. The research revealed some correlations between the maximum dry density of soils with the type of fines, the fines content and the Uniformity Coefficient. These correlations were measured and some particular behavioral trends were encountered and analyzed. It was found that well-graded sands have higher maximum dry density than poorly graded when the soils have the same fines content, also it was encountered that plastic fines tend to increase the maximum dry density.
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Date Issued
2004
Identifier
CFE0000261, ucf:46237
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000261
DESIGN, CHARACTERIZATION AND COMPACT MODELING OF NOVEL SILICON CONTROLLED RECTIFIER (SCR)-BASED DEVICES FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPLICATIONS IN INTEGRATED CIRCUITS
Title
DESIGN, CHARACTERIZATION AND COMPACT MODELING OF NOVEL SILICON CONTROLLED RECTIFIER (SCR)-BASED DEVICES FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPLICATIONS IN INTEGRATED CIRCUITS.
Creator
Lou, Lifang, Liou, Juin J., University of Central Florida
Abstract / Description
Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have...
Show moreElectrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.
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Date Issued
2008
Identifier
CFE0002374, ucf:47788
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002374