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- Title
- SOFT POWER AND HARD POWER APPROACHES IN U.S. FOREIGN POLICY: A CASE STUDY COMPARISON IN LATIN AMERICA.
- Creator
-
Weinbrenner, John, Dolan, Chris, University of Central Florida
- Abstract / Description
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The purpose of this study was to examine the effects of soft power versus hard power in U.S. policy towards Latin America. In recent years America's unipolar moment has been challenged from populist leaders in the region to its inability to get a handle on the flow of illegal immigrants and illicit drugs that reach its shores. This thesis is a step to understanding the difference between power and influence as well as the effects of hard power and soft power in U.S. foreign policy. A...
Show moreThe purpose of this study was to examine the effects of soft power versus hard power in U.S. policy towards Latin America. In recent years America's unipolar moment has been challenged from populist leaders in the region to its inability to get a handle on the flow of illegal immigrants and illicit drugs that reach its shores. This thesis is a step to understanding the difference between power and influence as well as the effects of hard power and soft power in U.S. foreign policy. A historical comparative case study analysis has been conducted utilizing the cases of FDR's Good Neighbor policy and Reagan's contra war policies. This qualitative approach examined specific short-term and long-term goals of each policy and analyzed each strategy's ability to achieve those stated goals. The results of the study reveal that both soft and hard power approaches can have positive as well as negative effects on American influence in Latin America.
Show less - Date Issued
- 2007
- Identifier
- CFE0001600, ucf:47175
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001600
- Title
- Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
- Creator
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Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
- Abstract / Description
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Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
Show less - Date Issued
- 2015
- Identifier
- CFE0006206, ucf:52889
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006206