Current Search:  High Voltage (x)

View All Items

  • CSV Spreadsheet
(1 - 6 of 6)
HIGH SLEW RATE HIGH-EFFICIENCY DC-DC CONVERTER
Title
HIGH SLEW RATE HIGH-EFFICIENCY DC-DC CONVERTER.
Creator
Wang, Xiangcheng, Issa, Batarseh, University of Central Florida
Abstract / Description
Active transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive...
Show moreActive transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive nonlinear control has been proposed to reduce delay times in the actual controller, which injects one nonlinear signal in transient periods and simplifies the linear controller design. Switching mode current compensator with nonlinear control in secondary side is proposed to eliminate the effect of opotocoupler, which reduces response times and simplifies the linear controller design in isolated DC-DC converters. A novel control method has been carried out in two-stage isolated DC-DC converter to simplify the control scheme and improve the transient response, allowing for high duty cycle operation and large step-down voltage ratio with high efficiency. A balancing winding network composed of small power rating components is used to mitigate the double pole-zero effect in complementary-controlled isolated DC-DC converter, which simplifies the linear control design and improves the transient response without delay time. A parallel post regulator (PPR) is proposed for wide range input isolated DC-DC converter with secondary side control, which provides small part of output power and most of them are handled by unregulated rectifier with high efficiency. PPR is easy to achieve ZVS in primary side both in wide range input and full load range due to 0.5 duty cycle. PPR has reduced conduction loss and reduced voltage rating in the secondary side due to high turn ratio transformer, resulting in up to 8 percent efficiency improvement in the prototype compared to conventional methods.
Show less
Date Issued
2006
Identifier
CFE0001123, ucf:46877
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001123
HIGH VOLTAGE BIAS TESTING AND DEGRADATION ANALYSIS OF PHOTOVOLTAIC MODULES
Title
HIGH VOLTAGE BIAS TESTING AND DEGRADATION ANALYSIS OF PHOTOVOLTAIC MODULES.
Creator
Hadagali, Vinaykumar, Dhere, Neelkanth, University of Central Florida
Abstract / Description
This thesis mainly focuses on two important aspects of the photovoltaic modules. The first aspect addressed the high voltage bias testing and data and degradation analysis of high voltage biased thin film photovoltaic modules. The second aspect addressed the issues of reliability and durability of crystalline silicon module. Grid-connected photovoltaic systems must withstand high voltage bias in addition to harsh environmental conditions such as intermittent solar irradiance, high humidity,...
Show moreThis thesis mainly focuses on two important aspects of the photovoltaic modules. The first aspect addressed the high voltage bias testing and data and degradation analysis of high voltage biased thin film photovoltaic modules. The second aspect addressed the issues of reliability and durability of crystalline silicon module. Grid-connected photovoltaic systems must withstand high voltage bias in addition to harsh environmental conditions such as intermittent solar irradiance, high humidity, heat and wind. a-Si:H thin-film photovoltaic modules with earlier generation SnO2:F transparent conducting oxide (TCO) on the front glass installed on the FSEC High Voltage Test Bed were monitored since December 2001. The data was collected on a daily basis and analyzed. The leakage currents for some chosen time period were calculated and compared with the measured values. Current-voltage characteristic measurements were carried out to check any reduction in the power. Samples were cored and extracted for analysis from one of the -600 V biased modules. Leakage currents in high-voltage-biased laminates specially prepared with improved SnO2:F TCO are being monitored in the hot and humid climate in Florida. Negatively-biased modules showed clear signs of delamination. The leakage currents in high-voltage biased photovoltaic modules are functions of both temperature and relative humidity. Photovoltaic module leakage conductance was found to be thermally stimulated with a characteristic activation energy that depends on relative humidity. The adhesional strength was lost completely in the damaged area. Leakage current values from support to ground in new, unframed laminates fabricated with improved SnO2:F TCO layer were ~100 times lower under the high voltage bias in hot and humid environment. Information on the failure of field deployed modules must be complemented with why and how the modules fail while considering the issues of reliability and durability of crystalline silicon module. At present, all the failure modes have not been identified and failure mechanisms have not been understood. Experience has shown that as the materials and processes are changed, reliability issues that apparently had been resolved resurface. A multicrystalline silicon photovoltaic module that was manufactured by a non-US company and that had shown >50% performance loss in field-deployment of <2 years in hot and dry climate were studied for degradation analysis in comparison with a mc-Si module that was manufactured by the same company and that performed well after 10 years of field-deployment in hot and humid climate.. I-V measurements were carried out to analyze the reduction in photovoltaic parameters. Solder bond strength in mc-Si photovoltaic modules were measured to understand early degradation of performance. Samples were cored and extracted for further analysis. Adhesional strength between the busline metallization and the silicon cell in a newer generation mc-Si photovoltaic module was found to be considerably lower than that in the earlier vintage module. These results can be useful for early detection and diagnosis of field reliability issues and could assist in establishing correlation between long-term field data and observations and accelerated environmental stress testing. It is suggested that more detailed study should be undertaken using unencapsulated strings of crystalline silicon modules so as to avoid complication due to encapsulant creeping beneath the ribbons.
Show less
Date Issued
2005
Identifier
CFE0000798, ucf:46563
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000798
EFFICIENCY IMPROVEMENT TECHNIQUES FOR HIGH VOLTAGE CAPACITOR CHARGING METHODS
Title
EFFICIENCY IMPROVEMENT TECHNIQUES FOR HIGH VOLTAGE CAPACITOR CHARGING METHODS.
Creator
Islas, Michael, Batarseh, Issa, University of Central Florida
Abstract / Description
The goal of this thesis is to design and fabricate a DC-to-DC converter for use in high-voltage capacitor charging applications. The primary objectives include increasing the efficiency and reducing the cost of traditional methods used for this application. Traditional methods were not designed specifically for high-voltage capacitor charging and were thus very primitive and exhibited lower efficiency. Prior methods made use of a high voltage power supply and a current limiting resistor or...
Show moreThe goal of this thesis is to design and fabricate a DC-to-DC converter for use in high-voltage capacitor charging applications. The primary objectives include increasing the efficiency and reducing the cost of traditional methods used for this application. Traditional methods were not designed specifically for high-voltage capacitor charging and were thus very primitive and exhibited lower efficiency. Prior methods made use of a high voltage power supply and a current limiting resistor or control scheme. The power supply would often only operate efficiently at a single voltage value and would thus function poorly over a range used in charging a capacitor. The resistor would also dissipate a fair amount of power, also limiting efficiency. This design makes use of a traditional flyback topology utilizing a controller developed specifically for this application, centering the design approach on the LT3750. Hence, taking full advantage of the efficiency improving control scheme it provides. Additionally, through the use of advanced techniques to eliminate noise and power losses, the efficiency may be significantly improved. A detailed theoretical analysis of the charger is also presented. The analysis will then be applied to optimization techniques to select ideal component values to meet specific design specifications. In this research, a specifically designed and developed prototype will be used to experimentally verify the theoretical work and optimization techniques.
Show less
Date Issued
2009
Identifier
CFE0002899, ucf:48025
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002899
DESIGN, CHARACTERIZATION AND COMPACT MODELING OF NOVEL SILICON CONTROLLED RECTIFIER (SCR)-BASED DEVICES FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPLICATIONS IN INTEGRATED CIRCUITS
Title
DESIGN, CHARACTERIZATION AND COMPACT MODELING OF NOVEL SILICON CONTROLLED RECTIFIER (SCR)-BASED DEVICES FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPLICATIONS IN INTEGRATED CIRCUITS.
Creator
Lou, Lifang, Liou, Juin J., University of Central Florida
Abstract / Description
Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have...
Show moreElectrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.
Show less
Date Issued
2008
Identifier
CFE0002374, ucf:47788
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002374
HIGH CURRENT DENSITY LOW VOLTAGE ISOLATED DC-DC CONVERTERSWITH FAST TRANSIENT RESPONSE
Title
HIGH CURRENT DENSITY LOW VOLTAGE ISOLATED DC-DC CONVERTERSWITH FAST TRANSIENT RESPONSE.
Creator
Yao, Liangbin, Batarseh, Issa, University of Central Florida
Abstract / Description
With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current...
Show moreWith the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.
Show less
Date Issued
2007
Identifier
CFE0001814, ucf:47336
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001814
Adaptive Architectural Strategies for Resilient Energy-Aware Computing
Title
Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
Creator
Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
Abstract / Description
Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
Show less
Date Issued
2015
Identifier
CFE0006206, ucf:52889
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006206