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HOT CARRIER EFFECT ON LDMOS TRANSISTORS
Title
HOT CARRIER EFFECT ON LDMOS TRANSISTORS.
Creator
Jiang, Liangjun, Yuan, Jiann S., University of Central Florida
Abstract / Description
One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices...
Show moreOne of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.
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Date Issued
2007
Identifier
CFE0001551, ucf:47148
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001551
STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY
Title
STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY.
Creator
Liu, Yi, Yuan, Jiann.S., University of Central Florida
Abstract / Description
As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to...
Show moreAs CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide tuning range, and high stability, and a mixer to up-convert or down-convert the signal with good linearity. However, the RF front-end circuit performance is very sensitive to the variation of device parameters. The experimental results show that device performance is degraded significantly subject to HC stress and BD. Therefore, RF front-end performance is degraded by HC and BD effects. With scaling and increasing chip power dissipation, operating temperatures for device have also been increasing. Another reliability concern, which is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias, arises when the operation temperature of devices increases. NBTI has received much attention in recent year and it is found that NIT is present for all stress conditions and NOT is found to occur at high VG. Therefore, the probability of BD in pMOSFET increases with temperature since trapped charges during the NBTI process increase, thus resulting in percolation, a main cause of oxide degradation. The above effects can cause significant degradations in transistors, thus leading to the shifts of RF performance. This dissertation focuses on the following aspects: (1) RF performance degradation in nMOSFET and pMOSFET due to hot carrier and soft breakdown effects are examined experimentally and will be used for circuit application in the future. (2) A modeling method to analyze the gate oxide breakdown effects on RF nMOSFET has been proposed. The device performance drifts due to gate oxide breakdown are examined, breakdown spot resistance and total gate capacitance are extracted before and after stress for 0.16 um CMOS technology. (3) LC voltage controlled oscillator (VCO) performance degradation due to gate oxide breakdown effect is evaluated. (4) NBTI, HCI and BD combined effects on RF performance degradation are investigated. A physical picture illustrating the NBTI induced BD process is presented. A model to evaluate the time-to-failure (TTF) during NBTI is developed. DCIV method is used to extract the densities of NIT and NOT. Measurements show that there is direct correlation between the steplike increase in the gate current and the oxide-trapped charge (NOT). However, Breakdown has nothing to do with interface traps (NIT). (5) It is found that the degradation due to NSH stress is more severe than that of NS stress at high temperature. A model aiming to evaluate the stress-induced degradation is also developed.
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Date Issued
2005
Identifier
CFE0000505, ucf:46465
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000505
THE EFFECT OF HOT CARRIER STRESS ON LOW NOISE AMPLIFIER RADIO FREQUENCY PERFORMANCE UNDER WEAK AND STRONG INVERSION
Title
THE EFFECT OF HOT CARRIER STRESS ON LOW NOISE AMPLIFIER RADIO FREQUENCY PERFORMANCE UNDER WEAK AND STRONG INVERSION.
Creator
Shen, Lin, Yuan, Jiann, University of Central Florida
Abstract / Description
This thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the...
Show moreThis thesis work is mainly focused on studying RF performance degradation of a low noise amplifier (LNA) circuit due to hot carrier effect (HCE) in both the weak and strong inversion regions. Since the figures of merit for the RF circuit characterization are gain, noise figure, input, and output matching, the LNA RF performance drift is evaluated in a Cadence SpectreRF simulator subject to these features. This thesis presents hot carrier induced degradation results of an LNA to show that the HCE phenomenon is one of the serious reliability issues in the aggressively scaled RF CMOS design, especially for long-term operation of these devices. The predicted degradation from simulation results can be used design reliable CMOS RF circuits.
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Date Issued
2006
Identifier
CFE0000952, ucf:46763
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000952
INVESTIGATION AND TRADE STUDY ON HOT CARRIER RELIABILITY OF THE PHEMT FOR DC AND RF PERFORMANCE
Title
INVESTIGATION AND TRADE STUDY ON HOT CARRIER RELIABILITY OF THE PHEMT FOR DC AND RF PERFORMANCE.
Creator
Steighner, Jason, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description
A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe...
Show moreA unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstrate the performance degradation that occurs after a period of operation in an accelerated stress regime-one hour of high drain voltage, low drain current stress. This stress regime and normal operation regime are then modeled through Sentaurus. Output characteristics are shown along with stress mechanisms within the device. Lastly, a means of simulating a PHEMT post-stress is introduced. The approach taken accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance are then investigated.
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Date Issued
2011
Identifier
CFE0003994, ucf:48659
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0003994
MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT
Title
MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT.
Creator
CUI, ZHI, Liou, Juin J., University of Central Florida
Abstract / Description
Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0...
Show moreLong-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
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Date Issued
2005
Identifier
CFE0000476, ucf:46360
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0000476
Adaptive Architectural Strategies for Resilient Energy-Aware Computing
Title
Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
Creator
Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
Abstract / Description
Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
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Date Issued
2015
Identifier
CFE0006206, ucf:52889
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006206