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(1 - 8 of 8)
- Title
- MODELING AND OPTIMIZATION OF BODY DIODE REVERSE RECOVERY CHARACTERISTICS OF LDMOS TRANSISTORS.
- Creator
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Deschaine, Wesley, Shen, John, University of Central Florida
- Abstract / Description
-
As switching speeds for DC-DC converter applications keep becoming faster and faster and voltage requirements become smaller and smaller, the need for new device structures becomes more prevalent. Designers of these new structures will need to make sure they take into consideration the different power losses associated with the different structures and make modifications to reduce or if possible eliminate them. A new 30V LDMOS device has been created and is being implemented into a...
Show moreAs switching speeds for DC-DC converter applications keep becoming faster and faster and voltage requirements become smaller and smaller, the need for new device structures becomes more prevalent. Designers of these new structures will need to make sure they take into consideration the different power losses associated with the different structures and make modifications to reduce or if possible eliminate them. A new 30V LDMOS device has been created and is being implemented into a synchronous buck converter for future DC-DC conversions. This new lateral device has a Figure of Merit of 80mÙ*nC, representing a 50% reduction from the conventional trench MOSFET. The only draw back with this new device is that the body diode power loss has increased significantly. There are two principal goals of this research. The first is to reduce the body diode reverse recovery characteristics of a 30V LDMOS transistor without employing an additional Schottky diode, increasing the Figure of Merit, or decreasing the breakdown voltage past 30 volts. The second is to achieve 75% reduction in reverse recovery charge (Qrr) through each solution. Four solutions will be presented in this study and have been verified through extensive ISE-TCAD device and circuit simulation.
Show less - Date Issued
- 2006
- Identifier
- CFE0001081, ucf:46778
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001081
- Title
- MODELING,DESIGN,AND CHARACTERIZATION OF MONOLITHIC BI-DIRECTIONAL POWER SEMICONDUCTOR SWITCH.
- Creator
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Fu, Yue, Shen, Z.John, University of Central Florida
- Abstract / Description
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Bidirectional power switching devices are needed in many power management applications, particularly in lithium-ion battery protection circuitry. A monolithic bidirectional power switch fabricated with a simplified CMOS technology is introduced in this dissertation. Throughout the design process, ISE TCAD tool plays an important role. Design variables are carefully analyzed to improve the device performance or yield the best trade off. Optimization is done with the help of TCAD simulation and...
Show moreBidirectional power switching devices are needed in many power management applications, particularly in lithium-ion battery protection circuitry. A monolithic bidirectional power switch fabricated with a simplified CMOS technology is introduced in this dissertation. Throughout the design process, ISE TCAD tool plays an important role. Design variables are carefully analyzed to improve the device performance or yield the best trade off. Optimization is done with the help of TCAD simulation and theoretical calculations. The device has been successfully fabricated using simplified 0.5 micron CMOS process. The experimental result shows a breakdown voltage of 25V. Due to the interdigitated source to source design, the inter-terminal current flowing path is effectively reduced to a few microns. The experimental result shows an ultra low specific on resistance. In comparison with other bi-directional power semiconductor switches by some major semiconductor manufacturers, the proposed BDS device has less than one half of the specific on resistance, thus substantially lower on state power loss of the switch. The proposed BDS device has a unique NPNPN structure, in comparison with NPNP structure, which is the analytical structure for CMOS latch-up, the proposed device inherently exhibits a better latch up immunity than CMOS inverter, thanks to the negative feed back mechanism of the extra NPN parasitic BJT transistor. In order to implement the device into simulators like PSPICE or Cadence IC Design, a compact model named variable resistance model has been built. This simple analytical model fits quite well with experimental data, and can be easily implemented by Verilog-A or other hardware description languages. Also, macro modeling is possible provided that the model parameters can be extracted from experimental curves. Several advanced types of BDS devices have been proposed, they exceed the basic BDS design in terms of breakdown voltage and /or on resistance. These advanced structures may be prominent for further improvement of the basic BDS device to a higher extend. Some cell phone providers such as Nokia is already asking for higher breakdown voltage of BDS device, due to the possibility of incidentally insert the battery pack into the cell phone with wrong pin polarity. Hopefully, the basic BDS design or one of these advanced types may eventually be implemented into the leading brand cell phone battery packs.
Show less - Date Issued
- 2007
- Identifier
- CFE0001605, ucf:47168
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001605
- Title
- HOT CARRIER EFFECT ON LDMOS TRANSISTORS.
- Creator
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Jiang, Liangjun, Yuan, Jiann S., University of Central Florida
- Abstract / Description
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One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices...
Show moreOne of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs.
Show less - Date Issued
- 2007
- Identifier
- CFE0001551, ucf:47148
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001551
- Title
- Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions.
- Creator
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Li, Hang, Sundaram, Kalpathy, Batarseh, Issa, Fan, Deliang, Gong, Xun, Salcedo, Javier, University of Central Florida
- Abstract / Description
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Electrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A...
Show moreElectrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation.Thermal failure is one of the main reasons to cause device failure under ESD conditions. A compact model is developed to predict thermal failure with circuit simulators. Instead of considering the detailed failure mechanisms, a failure temperature is introduced to indicate device failure. The developed model is implemented by a multiple-stage thermal network.P-N junction is the fundamental structure for ESD protection devices. An enhanced diode model is proposed and is used to simulate the device behaviors for ESD events. The model includes all physical effects for ESD conditions, which are voltage overshoot, self-heating effect, velocity saturation and thermal failure. The proposed model not only can fit the I-V and transient characteristics, but also can predict failure for different pulses.Safe Operating Area (SOA) is an important factor to evaluate the LDMOS performance. The transient SOA boundary is considered as power-defined. By placing the failure monitor under certain conditions, the developed modeling methodology can predict the boundary of transient SOA for any short pulse stress conditions. No matter failure happens before or after snapback phenomenon.Weibull distribution is popular to evaluate the dielectric lifetime for CVS. By using the transformative version of power law, the pulsing stresses are converted into CVS, and TDDB under ESD conditions for SiN MIMCAPs is analyzed. The thickness dependency and area independency of capacitor breakdown voltage is observed, which can be explained by the constant ?E model instead of conventional percolation model.
Show less - Date Issued
- 2019
- Identifier
- CFE0007670, ucf:52512
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007670
- Title
- STUDY OF INGAAS LDMOS FOR POWER CONVERSION APPLICATIONS.
- Creator
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Liu, Yidong, Yuan, Jiann S., University of Central Florida
- Abstract / Description
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In this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-μm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways,...
Show moreIn this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-μm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways, structure with the same cross-sectional dimension, and structure with different thickness of gate dielectric to achieve the same gate capacitance. The on-resistance of the new device shows a big improvement with no degradation on breakdown voltage over traditional device. Also it is indicated from these comparisons that the figure of merit(FOM) Ron·Qg of In0.65Ga0.35As LDMOS shows an average of 91.9% improvement to that of Si LDMOS. To further explore the benefit of using In0.65Ga0.35As LDMOS as switch in power applications, DC-DC buck converter is utilized to observe the performance of LDMOS in terms of power efficiency. The LDMOS performance is experimented with operation frequency of the circuit sweeping in the range from 100 KHz to 100 MHz. It turns out InGaAs LDMOS is good candidate for power applications.
Show less - Date Issued
- 2009
- Identifier
- CFE0002686, ucf:48217
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002686
- Title
- DESIGN AND MODELING OF RADIATION HARDENED LATERAL POWER MOSFETS.
- Creator
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Landowski, Matthew, Shen, Zheng, University of Central Florida
- Abstract / Description
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Galactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated...
Show moreGalactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated mix of photo-generated current, avalanche generated current, and activation of the inherent parasitic bipolar transistor. Current space-borne power systems lack the utility and advantages of terrestrial power systems. Vertical-double-diffused MOSFETs (VDMOS) is by far the most common power semiconductor device and are very susceptible to SEEs by their vertical structure. Modern space power switches typically require system designers to de-rate the power semiconductor switching device to account for this. Consequently, the power system suffers from increased size, cost, and decreased performance. Their switching speed is limited due to their vertical structure and cannot be used for MHz frequency applications limiting the use of modern digital electronics for space missions. Thus, the Power Semiconductor Research Laboratory at the University of Central Florida in conjunction with Sandia National Laboratories is developing a rad-hard by design lateral-double-diffused MOSFET (LDMOS). The study provides a novel in-depth physical analysis of the mechanisms that cause the LDMOS to burnout during an SEE and provides guidelines for making the LDMOS rad-hard to SEB. Total dose radiation, another important radiation effect, can cause threshold voltage shifts but is beyond the scope of this study. The devices presented have been fabricated with a known total dose radiation hard CMOS process. Single-event burnout data from simulations and experiments are presented in the study to prove the viability of using the LDMOS to replace the VDMOS for space power systems. The LDMOS is capable of higher switching speeds due to a reduced drain-gate feedback capacitance (Miller Capacitor). Since the device is lateral it is compatible with complimentary-metal-oxide-semiconductor (CMOS) processes, lowering developing time and fabrication costs. High switching frequencies permit the use of high density point-of-load conversion and provide a fast dynamic response.
Show less - Date Issued
- 2009
- Identifier
- CFE0002795, ucf:48113
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002795
- Title
- Lateral Power MOSFETs Hardened Against Single Event Radiation Effects.
- Creator
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Shea, Patrick, Shen, Zheng, Yuan, Jiann-Shiun, Malocha, Donald, University of Central Florida
- Abstract / Description
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The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard...
Show moreThe underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metrics.
Show less - Date Issued
- 2011
- Identifier
- CFE0004165, ucf:49044
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004165
- Title
- LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation.
- Creator
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Salih, Aiman, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Kapoor, Vikram, University of Central Florida
- Abstract / Description
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The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ...
Show moreThe benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance (&)#215; gate charge) of 5.93 m?-nC.
Show less - Date Issued
- 2017
- Identifier
- CFE0006955, ucf:51673
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006955
