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Title: STUDY OF ESD EFFECTS ON RF POWER AMPLIFIERS.
Creator: Narasimha Raju, Divya, Yuan, Jiann, University of Central Florida
Abstract / Description: Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even...
Show moreToday, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA's RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.
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Date Issued: 2011
Identifier: CFE0003630, ucf:48881
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003630

Title: RF LOW PASS FILTER DESIGN AND FABRICATION USING INTEGRATED PASSIVE DEVICE TECHNOLOGY.
Creator: Li, Heli, Wu, Thomas, University of Central Florida
Abstract / Description: In this thesis, the whole process of design a low pass filter (LPF) for the wireless communication application has been presented. Integrated passive device technology based on GaAs substrate has been utilized to make the LPF. Schematic simulation and electromagnetic simulations are extensively used in the design process. EM simulation is used in the selection of layout design and processing parameters for design optimization of both the inductors and IPD harmonic filters. The effective use...
Show moreIn this thesis, the whole process of design a low pass filter (LPF) for the wireless communication application has been presented. Integrated passive device technology based on GaAs substrate has been utilized to make the LPF. Schematic simulation and electromagnetic simulations are extensively used in the design process. EM simulation is used in the selection of layout design and processing parameters for design optimization of both the inductors and IPD harmonic filters. The effective use of EM simulation enables us to realize the successful development of high performance harmonic filters. To make the optimization be more flexible and also for a deeper understanding of the optimization theory, optimization using genetic algorithm is also implemented. The weight of each targets are adjustable, and a non-uniformly distributed goal for the harmonic rejection range is introduced to achieve better optimization results. The embedded LPF is built and measurement results show good agreement with the simulation data. This kind of very compact, high performance harmonic filters can be used in radio transceiver front-end modules. The realized harmonic filters have insertion loss less than 0.6 dB and harmonic rejections greater than 25 dB with a compact die size of 0.8 mm2.
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Date Issued: 2006
Identifier: CFE0001466, ucf:47091
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001466

Title: Design and Implementation of Silicon-Based MEMS Resonators for Application in Ultra Stable High Frequency Oscillators.
Creator: Shahraini, Sarah, Abdolvand, Reza, Gong, Xun, Sundaram, Kalpathy, Kapoor, Vikram, Rajaraman, Swaminathan, University of Central Florida
Abstract / Description: The focus of this work is to design and implement resonators for ultra-stable high-frequency ((>)100MHz) silicon-based MEMS oscillators. Specifically, two novel types of resonators are introduced that push the performance of silicon-based MEMS resonators to new limits. Thin film Piezoelectric-on-Silicon (TPoS) resonators have been shown to be suitable for oscillator applications due to their combined high quality factor, coupling efficiency, power handling and doping-dependent temperature...
Show moreThe focus of this work is to design and implement resonators for ultra-stable high-frequency ((>)100MHz) silicon-based MEMS oscillators. Specifically, two novel types of resonators are introduced that push the performance of silicon-based MEMS resonators to new limits. Thin film Piezoelectric-on-Silicon (TPoS) resonators have been shown to be suitable for oscillator applications due to their combined high quality factor, coupling efficiency, power handling and doping-dependent temperature-frequency behavior. This thesis is an attempt to utilize the TPoS platform and optimize it for extremely stable high-frequency oscillator applications.To achieve the said objective, two main research venues are explored. Firstly, quality factor is systematically studied and anisotropy of single crystalline silicon (SCS) is exploited to enable high-quality factor side-supported radial-mode (aka breathing mode) TPoS disc resonators through minimization of anchor-loss. It is then experimentally demonstrated that in TPoS disc resonators with tethers aligned to [100], unloaded quality factor improves from ~450 for the second harmonic mode at 43 MHz to ~11,500 for the eighth harmonic mode at 196 MHz. Secondly, thickness quasi-Lam(&)#233; modes are studied and demonstrated in TPoS resonators for the first time. It is shown that thickness quasi-Lam(&)#233; modes (TQLM) could be efficiently excited in silicon with very high quality factor (Q). A quality factor of 23.2 k is measured in vacuum at 185 MHz for a fundamental TQLM-TPoS resonators designed within a circular acoustic isolation frame. Quality factor of 12.6 k and 6 k are also measured for the second- and third- harmonic TQLM TPoS resonators at 366 MHz and 555 MHz respectively. Turn-over temperatures between 40 (&)deg;C to 125 (&)deg;C are also designed and measured for TQLM TPoS resonators fabricated on degenerately N-doped silicon substrates. The reported extremely high quality factor, very low motional resistance, and tunable turn-over temperatures (>)80 (&)#186;C make these resonators a great candidate for ultra-stable oven-controlled high-frequency MEMS oscillators.
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Date Issued: 2019
Identifier: CFE0007861, ucf:52775
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007861

Title: On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits.
Creator: Cui, Qiang, Liou, Juin, Yuan, Jiann-Shiun, Wu, Xinzhang, Haralambous, Michael, Shen, Zheng, Deppe, Dennis, University of Central Florida
Abstract / Description: Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD...
Show moreElectrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS.The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT's snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Post-snapback saturation is caused by temperature-induced mobility degradation due to III-V compound semiconductor materials' poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT's InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancement-mode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ((>) 5.2 A It2) under HBM. Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process.In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR's impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter.Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys.
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Date Issued: 2013
Identifier: CFE0004668, ucf:49848
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004668

Title: LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS MEMS SENSORS.
Creator: Sadat, Md Anwar, Yuan, Jiann, University of Central Florida
Abstract / Description: A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a...
Show moreA sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.
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Date Issued: 2004
Identifier: CFE0000304, ucf:46318
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000304

Title: MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT.
Creator: CUI, ZHI, Liou, Juin J., University of Central Florida
Abstract / Description: Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0...
Show moreLong-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
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Date Issued: 2005
Identifier: CFE0000476, ucf:46360
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000476

Title: RF Energy Harvesting for Implantable ICs with On-chip Antenna.
Creator: Liu, Yu-chun, Yuan, Jiann-Shiun, Gong, Xun, Jones, W, University of Central Florida
Abstract / Description: Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite...
Show moreNowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1(&)#215;1(&)#215;2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.
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Date Issued: 2014
Identifier: CFE0005202, ucf:50652
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005202

Title: ANALYSIS AND DESIGN OF MINIATURIZED RF SAW DUPLEXER PACKAGE.
Creator: Dong, Hao, Wu, Thomas, University of Central Florida
Abstract / Description: This dissertation provides a comprehensive methodology for accurate analysis and design of miniaturized radio frequency (RF) surface acoustic wave (SAW) duplexer package. Full-wave analysis based on the three dimensional (3-D) finite element method (FEM) is successfully applied to model the package. The die model is obtained by combining the acoustics and die busbars parasitics models. The acoustics model is obtained using the coupling-of-models (COM) technique. The die busbars, bonding wires...
Show moreThis dissertation provides a comprehensive methodology for accurate analysis and design of miniaturized radio frequency (RF) surface acoustic wave (SAW) duplexer package. Full-wave analysis based on the three dimensional (3-D) finite element method (FEM) is successfully applied to model the package. The die model is obtained by combining the acoustics and die busbars parasitics models. The acoustics model is obtained using the coupling-of-models (COM) technique. The die busbars, bonding wires and printed circuit board (PCB) are modeled using full-wave analysis. After that, the models of package, die, and bonding wires are assembled together to get the total response. To take into account the mutual couplings, the methodology is extended to model the package, die busbars, and bonding wires together. The advantages and disadvantages of the methodology are also discussed. Based on the methodology, the Korea personal communication system (KPCS) duplexer is analyzed and designed. The isolation of KPCS duplexer package is significantly improved by redesigning inner ground plane, bonding wire scheme and ground via. A KPCS duplexer package is designed and excellent transmitter to receiver isolation in the transmission band is achieved. Simulation and measurement results are compared, and excellent agreement is found. Although we focus on investigating the methods to improve the isolation, the passband performance is also improved. The methodology is also successfully used for flip chip duplexer. The simulation results from our assembling method match the measurement results very well. Optimization method is applied to improve the transmit band isolation. With the new package and die design, the transmit band isolation can be improved from -53.6 dB to -65.2 dB. Based on the new package, the effect of the Rx ground trace on the isolation is investigated and the transmit band isolation can achieve -67.3 dB with the modification of the Rx ground trace. The technique developed in this dissertation reduces the design cycle time greatly and can be applied to various RF SAW device packages.
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Date Issued: 2005
Identifier: CFE0000688, ucf:46493
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000688

Title: RESOURCE BANKING: AN ENERGY-EFFICIENT, RUN-TIME ADAPTIVE PROCESSOR DESIGN TECHNIQUE.
Creator: Staples, Jacob, Heinrich, Mark, University of Central Florida
Abstract / Description: From the earliest and simplest scalar computation engines to modern superscalar out-of-order processors, the evolution of computational machinery during the past century has largely been driven by a single goal: performance. In today's world of cheap, billion-plus transistor count processors and with an exploding market in mobile computing, a design landscape has emerged where energy efficiency, arguably more than any other single metric, determines the viability of a processor for a given...
Show moreFrom the earliest and simplest scalar computation engines to modern superscalar out-of-order processors, the evolution of computational machinery during the past century has largely been driven by a single goal: performance. In today's world of cheap, billion-plus transistor count processors and with an exploding market in mobile computing, a design landscape has emerged where energy efficiency, arguably more than any other single metric, determines the viability of a processor for a given application. The historical emphasis on performance has left modern processors bloated and over provisioned for everyday tasks in the hope that during computationally intensive periods some performance improvement will be observed. This work explores an energy-efficient processor design technique that ensures even a highly over provisioned out-of-order processor has only as many of its computational resources active as it requires for efficient computation at any given time. Specifically, this paper examines the feasibility of a dynamically banked register file and reorder buffer with variable banking policies that enable unused rename registers or reorder buffer entries to be voltage gated (turned off) during execution to save power. The impact of bank placement, turn-off and turn-on policies as well as rail stabilization latencies for this approach are explored for high-performance desktop and server designs as well as low-power mobile processors.
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Date Issued: 2011
Identifier: CFE0003991, ucf:48675
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003991

Title: TOWARD A REAL-TIME CELESTIAL BODY INFORMATION SYSTEM.
Creator: Guise, Brian, Proctor, Michael, University of Central Florida
Abstract / Description: The National Aeronautics and Space Administration maintains a challenging schedule of planned and on-going space exploration missions that extend to the outer reaches of our galaxy. New missions represent a huge investment, in terms of actual costs for equipment and support infrastructure, and personnel training. The success of a mission is critical considering both the monetary investment, and for manned missions, the lives which are put at risk. Tragedies involving Challenger, Columbia,...
Show moreThe National Aeronautics and Space Administration maintains a challenging schedule of planned and on-going space exploration missions that extend to the outer reaches of our galaxy. New missions represent a huge investment, in terms of actual costs for equipment and support infrastructure, and personnel training. The success of a mission is critical considering both the monetary investment, and for manned missions, the lives which are put at risk. Tragedies involving Challenger, Columbia, Apollo 7, and the near tragedy of Apollo 13 exemplify that space exploration is a dangerous endeavor, posing extreme environmental conditions on both equipment and personnel. NASA, the National Science Foundation' and numerous independent researchers indicate that predictive simulations have the potential to decrease risk and increase efficiency and effectiveness in space exploration activity. Simulations provide the capability to conduct planning and rehearsal of missions, allowing risk reducing designs and techniques to be discovered and tested. Real-time simulations may improve the quality of the response in a real-time crisis situation. The US Army developed Layered Terrain Format (LTF) database is a uniquely architected database approach that provides high fidelity representation of terrain and specialized terrain query functions that are optimized to support real-time simulations. This dissertation investigates the question; can the unique LTF database architecture be applied to the general problem of celestial body representation? And if so, what benefits might it bring for mission planners and personnel executing the mission? Due to data limitations, this research investigates these questions through a lunar analog setting involving S band and Earth-bound communication signals as might be needed to conduct manned and/or robotic mission on the moon. The target terrain data set includes portions of the Black Point Lava Flow in Arizona which will be used for NASA's 2010 Desert RATS analog studies. Applied Research Associates Inc, the developer of the LTF product, generated Black Point databases and made limited modifications to the LTF Viewer tool, RAVEN, which is used for visualization of the database. Through the results attained during this research it is concluded that LTF product does provide a useful simulation capability which could be used by mission personnel both in pre-mission planning and during mission execution. Additionally, LTF is shown to have application an information system, allowing geo-specific data of interest to the mission to be implemented within its layers. The Florida Space Research & Education Grant Program sponsored by FSGC, Space Florida and UCF provided a grant of $31,500 to perform this research.
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Date Issued: 2010
Identifier: CFE0003403, ucf:48424
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003403

Title: A LOW PHASE NOISE K-BAND OSCILLATOR UTILIZING AN EMBEDDED DIELECTRIC RESONATOR ON MULTILAYER HIGH FREQUENCY LAMINATES.
Creator: Subramanian, Ajay, Gong, Xun, University of Central Florida
Abstract / Description: K-Band (18 to 26 GHz) dielectric resonator oscillators are typically used as a local oscillator in most K-Band digital transmitter/receiver topologies. Traditionally, the oscillator itself is made up of an active device, a dielectric resonator termination network, and a passive load matching network. The termination network embodies a cylindrical high permittivity dielectric resonator that is coupled on the same plane as a current carrying transmission line. This configuration provides an...
Show moreK-Band (18 to 26 GHz) dielectric resonator oscillators are typically used as a local oscillator in most K-Band digital transmitter/receiver topologies. Traditionally, the oscillator itself is made up of an active device, a dielectric resonator termination network, and a passive load matching network. The termination network embodies a cylindrical high permittivity dielectric resonator that is coupled on the same plane as a current carrying transmission line. This configuration provides an adequate resonance needed for oscillation but has some limitations. In order to provide a high Q resonance the entire oscillator is placed in a metal box to prevent radiation losses. This increases the overall size of the device and makes it difficult to integrate in smaller transceiver topologies. Secondly, a tuning screw is required to help excite the dominant mode of the resonator to achieve the high Q response. This can cause problems in precision due to the mechanical jitter of the screw inherent in mobile devices. By embedding this resonator inside the substrate it is possible to realize a very high Q resonance at a desired frequency and remove the need for a metal cavity and tuning screw. An additional advantage can be seen in terms of overall size reduction of the oscillator circuit. To demonstrate the feasibility of utilizing a dielectric resonator embedded within a substrate, a K-Band oscillator proof of concept has been designed, fabricated, and tested. The oscillator is comprised of a low noise active transistor device, an embedded k-band dielectric resonator and a passive transmission line load network. All elements within the oscillator are optimized to produce a steady oscillation near 20 GHz. Preliminary investigations of a microstrip resonator S-band (2-3 GHz) oscillator are first discussed. Secondly, various challenges in design and fabrication are discussed. Thereafter, simulated and measured results of the embedded DRO structure are presented. Emphasis is placed on output oscillation power and low phase noise. With further development, the entire oscillator can be embedded within the substrate leaving only the active device on the surface. This allows for a considerable reduction in material cost and simple integration with miniaturized digital transmitter/receiver devices.
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Date Issued: 2008
Identifier: CFE0002451, ucf:47718
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002451

Title: "Design and Simulation of CMOS RF Active Mixers".
Creator: Gibson, Allen, Yuan, Jiann-Shiun, Wei, Lei, Sundaram, Kalpathy, University of Central Florida
Abstract / Description: This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage...
Show moreThis paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 (&)#181;m CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.
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Date Issued: 2011
Identifier: CFE0004112, ucf:49086
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004112

Title: CHARACTERIZATION OF ALUMINUM DOPED ZINC OXIDE THIN FILMS FOR PHOTOVOLTAIC APPLICATIONS.
Creator: Shantheyanda, Bojanna, Kalpathy, Sundaram, University of Central Florida
Abstract / Description: Growing demand for clean source of energy in the recent years has increased the manufacture of solar cells for converting sun energy directly into electricity. Research has been carried out around the world to make a cheaper and more efficient solar cell technology by employing new architectural designs and developing new materials to serve as light absorbers and charge carriers. Aluminum doped Zinc Oxide thin film, a Transparent conductive Oxides (TCO) is used as a window material in the...
Show moreGrowing demand for clean source of energy in the recent years has increased the manufacture of solar cells for converting sun energy directly into electricity. Research has been carried out around the world to make a cheaper and more efficient solar cell technology by employing new architectural designs and developing new materials to serve as light absorbers and charge carriers. Aluminum doped Zinc Oxide thin film, a Transparent conductive Oxides (TCO) is used as a window material in the solar cell these days. Its increased stability in the reduced ambient, less expensive and more abundance make it popular among the other TCOÃ‚Â's. It is the aim of this work to obtain a significantly low resistive ZnO:Al thin film with good transparency. Detailed electrical and materials studies is carried out on the film in order to expand knowledge and understanding. RF magnetron sputtering has been carried out at various substrate temperatures using argon, oxygen and hydrogen gases with various ratios to deposit this polycrystalline films on thermally grown SiO2 and glass wafer. The composition of the films has been determined by X-ray Photoelectron Spectroscopy and the identification of phases present have been made using X-ray diffraction experiment. Surface imaging of the film and roughness calculations are carried out using Scanning Electron Microscopy and Atomic Force Microscopy respectively. Determination of resistivity using 4-Probe technique and transparency using UV spectrophotometer were carried out as a part of electrical and optical characterization on the obtained thin film.The deposited thin films were later annealed in vacuum at various high temperatures and the change in material and electrical properties were analyzed.
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Date Issued: 2010
Identifier: CFE0003142, ucf:48623
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003142

Title: INVESTIGATION AND TRADE STUDY ON HOT CARRIER RELIABILITY OF THE PHEMT FOR DC AND RF PERFORMANCE.
Creator: Steighner, Jason, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe...
Show moreA unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstrate the performance degradation that occurs after a period of operation in an accelerated stress regime-one hour of high drain voltage, low drain current stress. This stress regime and normal operation regime are then modeled through Sentaurus. Output characteristics are shown along with stress mechanisms within the device. Lastly, a means of simulating a PHEMT post-stress is introduced. The approach taken accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance are then investigated.
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Date Issued: 2011
Identifier: CFE0003994, ucf:48659
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003994

Title: rf power amplifier and oscillator design for reliability and variability.
Creator: Chen, Shuyu, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Gong, Xun, Wang, Morgan, University of Central Florida
Abstract / Description: CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier...
Show moreCMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable.In this work, a class E power amplifier is designed and laid out using TSMC 0.18 (&)#181;m RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate self-heating effects under different localized heating situations. Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.
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Date Issued: 2013
Identifier: CFE0004664, ucf:49894
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004664

Title: STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES.
Creator: MA, JUN, Yuan, Jiann S., University of Central Florida
Abstract / Description: In the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused...
Show moreIn the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device – low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device – from device level to circuit level; Studying real voltage stress case – high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.
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Date Issued: 2009
Identifier: CFE0002856, ucf:48073
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002856

Title: RF Circuit Designs for Reliability and Process Variability Resilience.
Creator: Kritchanchai, Ekavut, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Wei, Lei, Lin, Mingjie, Chow, Lee, University of Central Florida
Abstract / Description: Complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms,...
Show moreComplementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms, such as gate oxide breakdown, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. In addition, process variability becomes a new design paradigm in modern RF circuits.In this Ph.D. work, a class F power amplifier (PA) was designed and analyzed using TSMC 180nm process technology. Its pre-layout and post-layout performances were compared. Post-layout parasitic effect decreases the output power and power-added efficiency. Physical insight of hot electron impact ionization and device self-heating was examined using the mixed-mode device and circuit simulation to mimic the circuit operating environment. Hot electron effect increases the threshold voltage and decreases the electron mobility of an n-channel transistor, which in turn decreases the output power and power-added efficiency of the power amplifier, as evidenced by the RF circuit simulation results. The device self-heating also reduces the output power and power-added efficiency of the PA. The process, voltage, and temperature (PVT) effects on a class AB power amplifier were studied. A PVT compensation technique using a current-source as an on-chip sensor was developed. The adaptive body bias design with the current sensing technique makes the output power and power-added efficiency much less sensitive to process variability, supply voltage variation, and temperature fluctuation, predicted by our derived analytical equations which are also verified by Agilent Advanced Design System (ADS) circuit simulation.Process variations and hot electron reliability on the mixer performance were also evaluated using different process corner models. The conversion gain and noise figure were modeled using analytical equations, supported by ADS circuit simulation results. A process invariant current source circuit was developed to eliminate process variation effect on circuit performance. Our conversion gain, noise figure, and output power show robust performance against PVT variations compared to those of a traditional design without using the current sensor, as evidenced by Monte Carlo statistical simulation.Finally, semiconductor process variations and hot electron reliability on the LC-voltage controlled oscillator (VCO) performance was evaluated using different process models. In our newly designed VCO, the phase noise and power consumptions are resilient against process variation effect due to the use of on-chip current sensing and compensation. Our Monte-Carlo simulation and analysis demonstrate that the standard deviation of phase noise in the new VCO design reduces about five times than that of the conventional design.
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Date Issued: 2016
Identifier: CFE0006131, ucf:51182
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006131

Title: CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
Creator: Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
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Date Issued: 2011
Identifier: CFE0003595, ucf:48861
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003595

Title: LIQUID CRYSTAL OPTICS FOR COMMUNICATIONS, SIGNAL PROCESSING AND 3-D MICROSCOPIC IMAGING.
Creator: Khan, Sajjad, Riza, Nabeel, University of Central Florida
Abstract / Description: This dissertation proposes, studies and experimentally demonstrates novel liquid crystal (LC) optics to solve challenging problems in RF and photonic signal processing, freespace and fiber optic communications and microscopic imaging. These include free-space optical scanners for military and optical wireless applications, variable fiber-optic attenuators for optical communications, photonic control techniques for phased array antennas and radar, and 3-D microscopic imaging. At the heart of...
Show moreThis dissertation proposes, studies and experimentally demonstrates novel liquid crystal (LC) optics to solve challenging problems in RF and photonic signal processing, freespace and fiber optic communications and microscopic imaging. These include free-space optical scanners for military and optical wireless applications, variable fiber-optic attenuators for optical communications, photonic control techniques for phased array antennas and radar, and 3-D microscopic imaging. At the heart of the applications demonstrated in this thesis are LC devices that are non-pixelated and can be controlled either electrically or optically. Instead of the typical pixel-by-pixel control as is custom in LC devices, the phase profile across the aperture of these novel LC devices is varied through the use of high impedance layers. Due to the presence of the high impedance layer, there forms a voltage gradient across the aperture of such a device which results in a phase gradient across the LC layer which in turn is accumulated by the optical beam traversing through this LC device. The geometry of the electrical contacts that are used to apply the external voltage will define the nature of the phase gradient present across the optical beam. In order to steer a laser beam in one angular dimension, straight line electrical contacts are used to form a one dimensional phase gradient while an annular electrical contact results in a circularly symmetric phase profile across the optical beam making it suitable for focusing the optical beam. The geometry of the electrical contacts alone is not sufficient to form the linear and the quadratic phase profiles that are required to either deflect or focus an optical beam. Clever use of the phase response of a typical nematic liquid crystal (NLC) is made such that the linear response region is used for the angular beam deflection while the high voltage quadratic response region is used for focusing the beam. Employing an NLC deflector, a device that uses the linear angular deflection, laser beam steering is demonstrated in two orthogonal dimensions whereas an NLC lens is used to address the third dimension to complete a three dimensional (3-D) scanner. Such an NLC deflector was then used in a variable optical attenuator (VOA), whereby a laser beam coupled between two identical single mode fibers (SMF) was mis-aligned away from the output fiber causing the intensity of the output coupled light to decrease as a function of the angular deflection. Since the angular deflection is electrically controlled, hence the VOA operation is fairly simple and repeatable. An extension of this VOA for wavelength tunable operation is also shown in this dissertation. A LC spatial light modulator (SLM) that uses a photo-sensitive high impedance electrode whose impedance can be varied by controlling the light intensity incident on it, is used in a control system for a phased array antenna. Phase is controlled on the Write side of the SLM by controlling the intensity of the Write laser beam which then is accessed by the Read beam from the opposite side of this reflective SLM. Thus the phase of the Read beam is varied by controlling the intensity of the Write beam. A variable fiber-optic delay line is demonstrated in the thesis which uses wavelength sensitive and wavelength insensitive optics to get both analog as well as digital delays. It uses a chirped fiber Bragg grating (FBG), and a 1xN optical switch to achieve multiple time delays. The switch can be implemented using the 3-D optical scanner mentioned earlier. A technique is presented for ultra-low loss laser communication that uses a combination of strong and weak thin lens optics. As opposed to conventional laser communication systems, the Gaussian laser beam is prevented from diverging at the receiving station by using a weak thin lens that places the transmitted beam waist mid-way between a symmetrical transmitter-receiver link design thus saving prime optical power. LC device technology forms an excellent basis to realize such a large aperture weak lens. Using a 1-D array of LC deflectors, a broadband optical add-drop filter (OADF) is proposed for dense wavelength division multiplexing (DWDM) applications. By binary control of the drive signal to the individual LC deflectors in the array, any optical channel can be selectively dropped and added. For demonstration purposes, microelectromechanical systems (MEMS) digital micromirrors have been used to implement the OADF. Several key systems issues such as insertion loss, polarization dependent loss, wavelength resolution and response time are analyzed in detail for comparison with the LC deflector approach. A no-moving-parts axial scanning confocal microscope (ASCM) system is designed and demonstrated using a combination of a large diameter LC lens and a classical microscope objective lens. By electrically controlling the 5 mm diameter LC lens, the 633 nm wavelength focal spot is moved continuously over a 48 ƒÝm range with measured 3-dB axial resolution of 3.1 ƒÝm using a 0.65 numerical aperture (NA) micro-objective lens. The ASCM is successfully used to image an Indium Phosphide twin square optical waveguide sample with a 10.2 ƒÝm waveguide pitch and 2.3 ƒÝm height and width. Using fine analog electrical control of the LC lens, a super-fine sub-wavelength axial resolution of 270 nm is demonstrated. The proposed ASCM can be useful in various precision three dimensional imaging and profiling applications.
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Date Issued: 2005
Identifier: CFE0000750, ucf:46596
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000750

RF (8)	+ -
reliability (4)	+ -
CMOS (3)	+ -
ESD (2)	+ -
RF circuit performance (2)	+ -

device reliability (2)	+ -
gate oxide breakdown effect (2)	+ -
hard breakdown (2)	+ -
hot electron (2)	+ -
soft breakdown (2)	+ -
Active Mixer (1)	+ -
Cadence (1)	+ -
Celestial Body Simulation (1)	+ -
Charge Injection (1)	+ -
DRO (1)	+ -
Dielectric Resonator (1)	+ -
Embedded Oscillator (1)	+ -
Full-wave Analysis (1)	+ -
GaAs (1)	+ -
Gilbert Cell (1)	+ -
HEMT (1)	+ -
High Q (1)	+ -
Hot electron (1)	+ -
Hot-Carrier (1)	+ -
IC (1)	+ -
IPD technology (1)	+ -
Interactive Simulation (1)	+ -
K-Band (1)	+ -
LPF (1)	+ -
Layered Terrain Database (1)	+ -

University of Central Florida (19)	+ -
Yuan, Jiann-Shiun (7)	+ -
Gong, Xun (4)	+ -
Sundaram, Kalpathy (4)	+ -
Shen, Zheng (2)	+ -

Wei, Lei (2)	+ -
Wu, Thomas (2)	+ -
Yuan, Jiann (2)	+ -
Abdolvand, Reza (1)	+ -
CUI, ZHI (1)	+ -
Chen, Shuyu (1)	+ -
Chow, Lee (1)	+ -
Cui, Qiang (1)	+ -
Deppe, Dennis (1)	+ -
Dong, Hao (1)	+ -
Gibson, Allen (1)	+ -
Guise, Brian (1)	+ -
Haralambous, Michael (1)	+ -
Heinrich, Mark (1)	+ -
Jones, W (1)	+ -
Kalpathy, Sundaram (1)	+ -
Kapoor, Vikram (1)	+ -
Khan, Sajjad (1)	+ -
Kritchanchai, Ekavut (1)	+ -
Li, Heli (1)	+ -
Lin, Mingjie (1)	+ -
Liou, Juin (1)	+ -
Liou, Juin J. (1)	+ -
Liu, Yidong (1)	+ -
Liu, Yu-chun (1)	+ -

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