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(1 - 4 of 4)
- Title
- THE ROLE OF FRABIN (FGD4) IN AGGRESSIVE PROSTATE CANCER.
- Creator
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Bossan, Alexia M, Chakrabarti, Ratna, University of Central Florida
- Abstract / Description
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A major problem in prostate cancer (PCa) management is the development of drug resistance. It is known that there are changes in PCa biology upon prolonged treatment with drugs, including anti-androgen drugs that alter cellular signaling processes leading to the development of castration resistant PCa. MicroRNAs (miRNAs) are regulatory molecules that modulate gene expression through inhibition of protein translation and modulate cellular functions. Altered expression of miRNAs is often noted...
Show moreA major problem in prostate cancer (PCa) management is the development of drug resistance. It is known that there are changes in PCa biology upon prolonged treatment with drugs, including anti-androgen drugs that alter cellular signaling processes leading to the development of castration resistant PCa. MicroRNAs (miRNAs) are regulatory molecules that modulate gene expression through inhibition of protein translation and modulate cellular functions. Altered expression of miRNAs is often noted in drug resistant cancer including PCa. Studies from our laboratory have identified a number of down-regulated miRNAs in PCa, including miR-l 7-92a miRNAs. Frabin (FGD4) is a target of the miR-l 7-92a cluster that was found to be up-regulated in PCa cells. For this paper's investigation, an FGD4 knockdown approach was used to identify the effects on cell viability, cell cycle progression, cell migration and drug sensitivity. Two PCa cells lines, LNCaP-104S (androgen sensitive) and PC-3 (androgen independent), were used for our studies. MTS assays for both cell lines showed significant reduction in cell viability following knockdown of FGD4 compared to transfection with control siRNAs. Cell cycle analysis revealed an arrest in the G2/M phase of the cells that were transfected with FGD4 siRNAs. Cell migration assays revealed a decrease in migration rate of PC-3 cells after knockdown, which supports the involvement of FGD4 in actin- cytoskeleton rearrangement. Treatments with anti-mitotic drug Docetaxel (PC-3) or androgen receptor antagonist bicalutamide/Casodex (LNCaP-104S) showed improved sensitivity of the FGD4 siRNA treated cells to these drugs. Our results suggest the potential for FGD4 knockdown to be used in combination with currently used drugs, increasing the effectiveness of frontline chemotherapeutics.
Show less - Date Issued
- 2017
- Identifier
- CFH2000162, ucf:45937
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFH2000162
- Title
- TRACKING ERROR OF LEVERAGED AND INVERSE ETFS.
- Creator
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Romano, John, Gilkeson, Jim, University of Central Florida
- Abstract / Description
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Tracking ability of leveraged and inverse exchange traded funds can be very important to investors looking for a dependable return. If the investor wants to put their money on a certain index they feel strongly about, they expect their investment vehicle to track that return appropriately. Over the years, we have seen tremendous growth in the exchange traded fund industry. In 2006, leveraged and inverse funds were introduced to the market, allowing investors to take leveraged and directional...
Show moreTracking ability of leveraged and inverse exchange traded funds can be very important to investors looking for a dependable return. If the investor wants to put their money on a certain index they feel strongly about, they expect their investment vehicle to track that return appropriately. Over the years, we have seen tremendous growth in the exchange traded fund industry. In 2006, leveraged and inverse funds were introduced to the market, allowing investors to take leveraged and directional trades on indices. These investment vehicles can be traded as easily as any stock, and therefore need some attention. Since any novice investor can access and trade these funds, they need to be aware of the risks they are taking. In this study, I test whether the ProShares S&P tracking leveraged and inverse exchange traded funds track their appropriate index multiple as promised. I did this by running regressions on each fund against the appropriate multiple of their underlying indices. I did this for funds of different market capitalization, for different holding periods, and with different amounts of leverage, to compare how these funds track in different conditions. I found that the large cap funds tend to track the best, with the small cap funds tracking the worst. I also find that tracking error tends to increase with longer holding periods. I find that the distribution of excess returns becomes less normal over longer holding periods, and begins to flatten out and widen. There does not seem to be a concrete conclusion as to whether or not the amount of leverage affects the tracking ability of the funds. I end up with mixed results when comparing amounts of leverage by model fit and by tracking error. Direction also does not seem to play any role in the tracking ability of these funds.
Show less - Date Issued
- 2012
- Identifier
- CFH0004184, ucf:44893
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFH0004184
- Title
- A NEW FRAMEWORK FOR QOS PROVISIONING IN WIRELESS LANS USING THE P-PERSISTENT MAC PROTOCOL.
- Creator
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Anna, Kiran Babu, Bassiouni, Mostafa, University of Central Florida
- Abstract / Description
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The support of multimedia traffic over IEEE 802.11 wireless local area networks (WLANs) has recently received considerable attention. This dissertation has proposed a new framework that provides efficient channel access, service differentiation and statistical QoS guarantees in the enhanced distributed channel access (EDCA) protocol of IEEE 802.11e. In the first part of the dissertation, the new framework to provide QoS support in IEEE 802.11e is presented. The framework uses three...
Show moreThe support of multimedia traffic over IEEE 802.11 wireless local area networks (WLANs) has recently received considerable attention. This dissertation has proposed a new framework that provides efficient channel access, service differentiation and statistical QoS guarantees in the enhanced distributed channel access (EDCA) protocol of IEEE 802.11e. In the first part of the dissertation, the new framework to provide QoS support in IEEE 802.11e is presented. The framework uses three independent components, namely, a core MAC layer, a scheduler, and an admission control. The core MAC layer concentrates on the channel access mechanism to improve the overall system efficiency. The scheduler provides service differentiation according to the weights assigned to each Access Category (AC). The admission control provides statistical QoS guarantees. The core MAC layer developed in this dissertation employs a P-Persistent based MAC protocol. A weight-based fair scheduler to obtain throughput service differentiation at each node has been used. In wireless LANs (WLANs), the MAC protocol is the main element that determines the efficiency of sharing the limited communication bandwidth of the wireless channel. In the second part of the dissertation, analytical Markov chain models for the P-Persistent 802.11 MAC protocol under unsaturated load conditions with heterogeneous loads are developed. The Markov models provide closed-form formulas for calculating the packet service time, the packet end-to-end delay, and the channel capacity in the unsaturated load conditions. The accuracy of the models has been validated by extensive NS2 simulation tests and the models are shown to give accurate results. In the final part of the dissertation, the admission control mechanism is developed and evaluated. The analytical model for P-Persistent 802.11 is used to develop a measurement-assisted model-based admission control. The proposed admission control mechanism uses delay as an admission criterion. Both distributed and centralized admission control schemes are developed and the performance results show that both schemes perform very efficiently in providing the QoS guarantees. Since the distributed admission scheme control does not have a complete state information of the WLAN, its performance is generally inferior to the centralized admission control scheme. The detailed performance results using the NS2 simulator have demonstrated the effectiveness of the proposed framework. Compared to 802.11e EDCA, the scheduler consistently achieved the desired throughput differentiation and easy tuning. The core MAC layer achieved better delays in terms of channel access, average packet service time and end-to-end delay. It also achieved higher system throughput than EDCA for any given service differentiation ratio. The admission control provided the desired statistical QoS guarantees.
Show less - Date Issued
- 2010
- Identifier
- CFE0003243, ucf:48513
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003243
- Title
- DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
- Creator
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SALCEDO, Javier, Liou, Juin, University of Central Florida
- Abstract / Description
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The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
Show less - Date Issued
- 2006
- Identifier
- CFE0001213, ucf:46942
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001213
