Current Search: cascode (x)
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Title
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CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY.
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Creator
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Kutty, Karan, Yuan, Jiann-Shiun, University of Central Florida
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Abstract / Description
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This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were...
Show moreThis study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
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Date Issued
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2010
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Identifier
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CFE0003360, ucf:48477
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Format
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Document (PDF)
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PURL
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http://purl.flvc.org/ucf/fd/CFE0003360
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Title
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CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT.
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Creator
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Skaria, Giji, Yuan, Jiann, University of Central Florida
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Abstract / Description
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This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and...
Show moreThis study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18[micro]m CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
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Date Issued
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2011
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Identifier
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CFE0004030, ucf:49161
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Format
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Document (PDF)
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PURL
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http://purl.flvc.org/ucf/fd/CFE0004030
