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Electronic and Optoelectronic Transport Properties of Carbon Nanotube/Organic Semiconductor Devices
Title
Electronic and Optoelectronic Transport Properties of Carbon Nanotube/Organic Semiconductor Devices.
Creator
Sarker, Biddut, Khondaker, Saiful, Schulte, Alfons, Stolbov, Sergey, Gesquiere, Andre, University of Central Florida
Abstract / Description
Organic field effect transistors (OFETs) are of significant research interest due to their promising applications in large area, low-cost electronic devices such as flexible displays, sensor arrays, and radio-frequency identification tags. A major bottleneck in fabricating high-performance OFET is the large interfacial barrier between the metal electrodes and organic semiconductors (OSC) which results in an inefficient charge injection. Carbon nanotubes (CNTs) are considered to be a promising...
Show moreOrganic field effect transistors (OFETs) are of significant research interest due to their promising applications in large area, low-cost electronic devices such as flexible displays, sensor arrays, and radio-frequency identification tags. A major bottleneck in fabricating high-performance OFET is the large interfacial barrier between the metal electrodes and organic semiconductors (OSC) which results in an inefficient charge injection. Carbon nanotubes (CNTs) are considered to be a promising electrode material which can address this challenge.In this dissertation, we demonstrate fabrication of high-performance OFETs using aligned array CNT electrodes and investigate the detailed electronic transport properties of the fabricated devices. The OFETs with CNT electrodes show a remarkable enhancement in the device performance such as high mobility, high current on-off ratio, higher cutoff frequency, absence of short channel effect and better charge carrier injection than those OFETs with metal electrodes. From the low temperature transport measurements, we show that the charge injection barrier at CNT/OSC interface is smaller than that of the metal/OSC interface. A transition from direct tunneling to Fowler-Nordheim tunneling observed in CNT/OSC system shows further evidence of low injection barrier. A lower activation energy measured for the OFETs with CNT electrodes gives evidence of lower interfacial trap states. Finally, OFETs are demonstrated by directly growing crystalline organic nanowires on aligned array CNT electrodes.In addition to investigating the interfacial barrier at CNT/OSC interface, we also studied photoconduction mechanism of the CNT and CNT/OSC nanocomposite thin film devices. We found that the photoconduction is due to the exciton dissociations and charge carrier separation caused by a Schottky barrier at the metallic electrode/CNT interface and diffusion of the charge carrier through percolating CNT networks. In addition, it is found that photoresponse of the CNT/organic semiconductor can be tuned by changing the weight percentage of CNT into the organic semiconductors.
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Date Issued
2012
Identifier
CFE0004596, ucf:49217
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0004596
Nanoelectronic Devices using Carbon Nanotubes and Graphene Electrodes: Fabrication and Electronic Transport Investigations
Title
Nanoelectronic Devices using Carbon Nanotubes and Graphene Electrodes: Fabrication and Electronic Transport Investigations.
Creator
Kang, Narae, Khondaker, Saiful, Leuenberger, Michael, Zhai, Lei, University of Central Florida
Abstract / Description
Fabrication of high-performance electronic devices using the novel semiconductors is essential for developing future electronics which can be applicable in large-area, flexible and transparent displays, sensors and solar cells. One of the major bottlenecks in the fabrication of high-performance devices is a large interfacial barrier formation at metal/semiconductor interface originated from Schottky barrier and interfacial dipole barrier which causes inefficient charge injection at the...
Show moreFabrication of high-performance electronic devices using the novel semiconductors is essential for developing future electronics which can be applicable in large-area, flexible and transparent displays, sensors and solar cells. One of the major bottlenecks in the fabrication of high-performance devices is a large interfacial barrier formation at metal/semiconductor interface originated from Schottky barrier and interfacial dipole barrier which causes inefficient charge injection at the interface. Therefore, having a favorable contact at electrode/semiconductor is highly desirable for high-performance devices fabrication.In this dissertation, the fabrication of nanoelectronic devices and investigation of their transport properties using carbon nanotubes (CNTs) and graphene as electrode materials will be shown. I investigated two types of devices using (i) semiconducting CNTs, and (ii) organic semiconductors (OSC). In the first part of this thesis, I will demonstrate the fabrication of high-performance solution-processed highly enriched (99%) semiconducting CNT thin film transistors (s-CNT TFTs) using densely aligned arrays of metallic CNTs (m-CNTs) for source/drain electrodes. From the electronic transport measurements at room temperature, significant improvements of field-effect mobility, on-conductance, transconductance and current on/off ratio for m-CNT/s-CNT devices were found compared to control palladium (Pd contacted s-CNT devices. From the temperature dependent transport investigation, a lower Schottky barrier height for the m-CNT/s-CNT devices was found compared to the devices with control metal electrodes. The enhanced device performance can be attributed to the unique device geometry as well as strong ?- ? interaction at m-CNT/s-CNT interfaces. In addition, I also investigated s-CNT TFTs using reduced graphene oxide (RGO) electrodes.In the second part of my thesis, I will demonstrate high-performance organic field-effect transistors (OFETs) using different types of graphene electrodes. I show that the performance of OFETs with pentacene as OSC and RGO as electrode can be continuously improved by increasing the carbon sp2 fraction of RGO. The carbon sp2 fractions of RGO were varied by controlling the reduction time. When compared to control Pd electrodes, the mobility of the OFETs shows an improvement of ?200% for 61% sp2 fraction RGO, which further improves to ?500% for 80% RGO electrode. Similarly, I show that when the chemical vapor deposition (CVD) graphene film is used as electrodes in fabricating OFET, the better performance is observed in comparison to RGO electrodes. Our study suggests that, in addition to ?-? interaction at graphene/pentacene interface, the tunable electronic properties of graphene as electrode have a significant role in OFETs performance. For a fundamental understanding of the interface, we fabricated short-channel OFETs with sub-100nm channel length using graphene electrode. From the low temperature electronic transport measurements, a lower charge injection barrier was found compared to control metal electrode. The detailed investigations reported in this thesis clearly indicated that the use of CNT and graphene as electrodes can improve the performance of future nanoelectronic devices.
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Date Issued
2015
Identifier
CFE0006039, ucf:50982
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006039
FABRICATION AND TRANSPORT STUDIES OF N-TYPE ORGANIC FIELD EFFECT TRANSISTORS USING ALIGNED ARRAY CARBON NANOTUBES ELECTRODES
Title
FABRICATION AND TRANSPORT STUDIES OF N-TYPE ORGANIC FIELD EFFECT TRANSISTORS USING ALIGNED ARRAY CARBON NANOTUBES ELECTRODES.
Creator
Jimenez, Edwards, Khondaker, Saiful, University of Central Florida
Abstract / Description
We present fabrication of n-type organic field effect transistors (OFETs) using densely aligned array carbon nanotube (CNT) electrodes. The CNTs were aligned with a high linear density via dielectrophoresis (DEP) from an aqueous solution. In order to fabricate the CNT electrodes, aligned CNTs were cut by using electron beam lithography (EBL) and precise oxygen plasma etching. The n-type OFETs were fabricated in a bottom-contact configuration by depositing a thin film of C60 molecules between...
Show moreWe present fabrication of n-type organic field effect transistors (OFETs) using densely aligned array carbon nanotube (CNT) electrodes. The CNTs were aligned with a high linear density via dielectrophoresis (DEP) from an aqueous solution. In order to fabricate the CNT electrodes, aligned CNTs were cut by using electron beam lithography (EBL) and precise oxygen plasma etching. The n-type OFETs were fabricated in a bottom-contact configuration by depositing a thin film of C60 molecules between the CNT source and drain electrodes, and compared against a controlled C60 OFET with gold electrodes. The electron transport measurements of the OFETs using CNT electrodes show better transistor characteristics compared to OFETs using gold electrodes due to improved charge injection from densely aligned and open-ended nanotube tips.
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Date Issued
2012
Identifier
CFH0004217, ucf:44941
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFH0004217
"Design and Simulation of CMOS RF Active Mixers"
Title
"Design and Simulation of CMOS RF Active Mixers".
Creator
Gibson, Allen, Yuan, Jiann-Shiun, Wei, Lei, Sundaram, Kalpathy, University of Central Florida
Abstract / Description
This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage...
Show moreThis paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 (&)#181;m CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.
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Date Issued
2011
Identifier
CFE0004112, ucf:49086
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0004112
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES
Title
DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES.
Creator
SALCEDO, Javier, Liou, Juin, University of Central Florida
Abstract / Description
The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the...
Show moreThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
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Date Issued
2006
Identifier
CFE0001213, ucf:46942
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0001213