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USABILITY OF VARIOUS INPUT DEVICES ON A STEERING TASK
Title
USABILITY OF VARIOUS INPUT DEVICES ON A STEERING TASK.
Creator
Fund, Ian, McConnell, Daniel, University of Central Florida
Abstract / Description
In this study we examined the differences of performance of various input devices on a steering task. Two paths were created, one easy and one hard, with the harder path having more turning points to navigate with one of three different input devices: mouse and keyboard, Xbox 360 controller, and a joystick. Participants were also exposed to low or high stress conditions. High stress was caused by playing loud short bursts of music over headphones worn by participants during testing. Results...
Show moreIn this study we examined the differences of performance of various input devices on a steering task. Two paths were created, one easy and one hard, with the harder path having more turning points to navigate with one of three different input devices: mouse and keyboard, Xbox 360 controller, and a joystick. Participants were also exposed to low or high stress conditions. High stress was caused by playing loud short bursts of music over headphones worn by participants during testing. Results indicated the mouse and keyboard performed better in all cases. There was no significant difference between the Xbox controller and joystick. No differences were found in the low and high stress conditions. Differences in sex were found, even when controlling for video game experience. These findings indicate that the mouse and keyboard is the best device to use on a steering task.
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Date Issued
2015
Identifier
CFH0004763, ucf:45362
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFH0004763
GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs
Title
GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs.
Creator
Binder, Andrew, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Roy, Tania, Kapoor, Vikram, Chow, Lee, University of Central Florida
Abstract / Description
GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is...
Show moreGaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ((<) 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition.
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Date Issued
2019
Identifier
CFE0007885, ucf:52786
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0007885
STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES
Title
STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES.
Creator
MA, JUN, Yuan, Jiann S., University of Central Florida
Abstract / Description
In the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused...
Show moreIn the modern semiconductor world, there is a significant scaling of the transistor dimensions –The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device – low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device – from device level to circuit level; Studying real voltage stress case – high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.
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Date Issued
2009
Identifier
CFE0002856, ucf:48073
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002856
RF Circuit Designs for Reliability and Process Variability Resilience
Title
RF Circuit Designs for Reliability and Process Variability Resilience.
Creator
Kritchanchai, Ekavut, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Wei, Lei, Lin, Mingjie, Chow, Lee, University of Central Florida
Abstract / Description
Complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms,...
Show moreComplementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms, such as gate oxide breakdown, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. In addition, process variability becomes a new design paradigm in modern RF circuits.In this Ph.D. work, a class F power amplifier (PA) was designed and analyzed using TSMC 180nm process technology. Its pre-layout and post-layout performances were compared. Post-layout parasitic effect decreases the output power and power-added efficiency. Physical insight of hot electron impact ionization and device self-heating was examined using the mixed-mode device and circuit simulation to mimic the circuit operating environment. Hot electron effect increases the threshold voltage and decreases the electron mobility of an n-channel transistor, which in turn decreases the output power and power-added efficiency of the power amplifier, as evidenced by the RF circuit simulation results. The device self-heating also reduces the output power and power-added efficiency of the PA. The process, voltage, and temperature (PVT) effects on a class AB power amplifier were studied. A PVT compensation technique using a current-source as an on-chip sensor was developed. The adaptive body bias design with the current sensing technique makes the output power and power-added efficiency much less sensitive to process variability, supply voltage variation, and temperature fluctuation, predicted by our derived analytical equations which are also verified by Agilent Advanced Design System (ADS) circuit simulation.Process variations and hot electron reliability on the mixer performance were also evaluated using different process corner models. The conversion gain and noise figure were modeled using analytical equations, supported by ADS circuit simulation results. A process invariant current source circuit was developed to eliminate process variation effect on circuit performance. Our conversion gain, noise figure, and output power show robust performance against PVT variations compared to those of a traditional design without using the current sensor, as evidenced by Monte Carlo statistical simulation.Finally, semiconductor process variations and hot electron reliability on the LC-voltage controlled oscillator (VCO) performance was evaluated using different process models. In our newly designed VCO, the phase noise and power consumptions are resilient against process variation effect due to the use of on-chip current sensing and compensation. Our Monte-Carlo simulation and analysis demonstrate that the standard deviation of phase noise in the new VCO design reduces about five times than that of the conventional design.
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Date Issued
2016
Identifier
CFE0006131, ucf:51182
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006131
Investigation of Novel Fin Structures Enhancing Micro Heat Sink Thermal Performance
Title
Investigation of Novel Fin Structures Enhancing Micro Heat Sink Thermal Performance.
Creator
Ismayilov, Fuad, Peles, Yoav, Kassab, Alain, Putnam, Shawn, Akturk, Ali, University of Central Florida
Abstract / Description
Operating temperature in electronics applications is continuously increasing. Therefore, for the past few decades, high heat flux removing micro heat sinks are investigated in terms of heat transfer effectiveness. This study generally concentrates on improving the passive heat transfer techniques. Micro heat sinks used in experiments are fabricated using MEMS techniques. Resistance temperature detectors, RTDs, were used for temperature measurements. The experimental data was obtained for...
Show moreOperating temperature in electronics applications is continuously increasing. Therefore, for the past few decades, high heat flux removing micro heat sinks are investigated in terms of heat transfer effectiveness. This study generally concentrates on improving the passive heat transfer techniques. Micro heat sinks used in experiments are fabricated using MEMS techniques. Resistance temperature detectors, RTDs, were used for temperature measurements. The experimental data was obtained for single and two phase flow regions; however, only single phase flow results were considered in numerical simulations. Numerical validations were performed on the micro heat sinks, including cylinder and hydrofoil shaped pin fins. Following the validation phase, optimization has been performed to further improve the hydraulic and thermal performance. DOE study showed that the chord length and leading edge size of the hydrofoil pin fin are significant contributors to the thermal performance. The ranges of geometrical variables were identified and fed into multi-objective optimization cycles implementing the multi-objective genetic algorithm. The optimization objectives were to minimize pumping requirements while enhancing the local and global heat transfer effectiveness over the surface of the heater in single phase flow environment. A broad range of geometries were obtained with an acceptable tradeoff between thermal and hydraulic performance for low Reynolds number. Additionally, tandem geometries were investigated and showed that higher heat transfer effectiveness could be obtained with acceptable pumping power requirements. The importance of such optimization studies before the experimental testing is highlighted, and novel geometries are presented for further experimental investigations. Thermal performance improvement of 28% was obtained via implementing proposed geometries with only a 12% pressure drop increase. Local heat transfer optimization, aiming to decrease the local temperatures were also performed using doublet pin fin configurations. Results showed that tandem hydrofoils could control the flow with minimum pressure drops while reaching the desired low local temperatures.
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Date Issued
2019
Identifier
CFE0007821, ucf:52828
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0007821