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INTEGRATED OPTICAL SPR (SURFACE PLASMON RESONANCE) SENSOR BASED ON OPTOELECTRONIC PLATFORM
Title
INTEGRATED OPTICAL SPR (SURFACE PLASMON RESONANCE) SENSOR BASED ON OPTOELECTRONIC PLATFORM.
Creator
Bang, Hyungseok, LiKamWa, Patrick, University of Central Florida
Abstract / Description
Current major demands in SPR sensor development are system miniaturization and throughput improvement. Structuring an array of integrated optical SPR sensor heads on a semiconductor based optoelectronic platform could be a promising solution for those issues, since integrated optical waveguides have highly miniaturized dimension and the optoelectronic platform enables on-chip optical-to-electrical signal conversion. Utilizing a semiconductor based platform to achieve optoelectronic...
Show moreCurrent major demands in SPR sensor development are system miniaturization and throughput improvement. Structuring an array of integrated optical SPR sensor heads on a semiconductor based optoelectronic platform could be a promising solution for those issues, since integrated optical waveguides have highly miniaturized dimension and the optoelectronic platform enables on-chip optical-to-electrical signal conversion. Utilizing a semiconductor based platform to achieve optoelectronic functionality poses requirements to the senor head; the sensor head needs to have reasonably small size while it should have reasonable sensitivity and fabrication tolerance. This research proposes a novel type of SPR sensor head and demonstrates a fabricated device with an array of integrated optical SPR sensor heads endowed with optoelectronic functionality. The novel integrated optical SPR sensor head relies on mode conversion efficiency for its operational principle. The beauty of this type of sensor head is it can produce clear contrast in SPR spectrum with a highly miniaturized and simple structure, in contrast to several-millimeter-scale conventional absorption type or interferometer type sensor heads. The integrated optical SPR sensor with optoelectronic functionality has been realized by structuring a dielectric waveguide based SPR sensor head on a photodetector-integrated semiconductor substrate. A large number of unit sensors have been fabricated on a substrate with a batch fabrication process, which promises a high throughput SPR sensor system or low-priced disposable sensors.
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Date Issued
2008
Identifier
CFE0002312, ucf:47841
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0002312
A Solid Phase Assay for Topoisomerase I interfacial Poisons and Catalytic Inhibitors
Title
A Solid Phase Assay for Topoisomerase I interfacial Poisons and Catalytic Inhibitors.
Creator
Cyril Sagayaraj, Vidusha, Muller, Mark, Zhao, Jihe, Chakrabarti, Debopam, University of Central Florida
Abstract / Description
We report a mechanism based screening technique to rapidly identify eukaryotic topoisomerase I targeting agents. The method is based on genetic tagging of topoisomerase I to immobilize the enzyme on a solid surface in a microtiter well format. DNA is added to the wells and retained DNA is detected by Picogreen fluorescence. Compounds that result in an increase in Picogreen staining represent potential topoisomerase interfacial poisons while those that reduce fluorescence report catalytic...
Show moreWe report a mechanism based screening technique to rapidly identify eukaryotic topoisomerase I targeting agents. The method is based on genetic tagging of topoisomerase I to immobilize the enzyme on a solid surface in a microtiter well format. DNA is added to the wells and retained DNA is detected by Picogreen fluorescence. Compounds that result in an increase in Picogreen staining represent potential topoisomerase interfacial poisons while those that reduce fluorescence report catalytic inhibitors; therefore, the solid phase assay represents a 'bimodal' readout that reveals mechanisms of action. The method has been demonstrated to work with known interfacial poisons and catalytic inhibitors. In addition to specific topoisomerase targeting drugs, the method also weakly detects other relevant anticancer agents, such as potent DNA alkylating and intercalating compounds; therefore, topoisomerase I HTS represents an excellent tool for searching and identifying novel genotoxic agents. This method is rapid, robust, economical and scalable for large library screens.
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Date Issued
2011
Identifier
CFE0004473, ucf:49304
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0004473
Multi-target high-throughput screening assays for antimicrobial drug discovery
Title
Multi-target high-throughput screening assays for antimicrobial drug discovery.
Creator
Grube, Christopher, Roy, Herve, Chakrabarti, Debopam, Moore, Sean, Koculi, Eda, University of Central Florida
Abstract / Description
The rise of antibiotic resistant microbes (bacteria, fungi, and parasites), combined with the current void of new drugs entering the clinical setting, has created an urgent need for the discovery of new antimicrobials. High-throughput screening (HTS) assays represent a fast and cost-efficient method for identifying new therapeutic compounds and have been the longstanding gold standard for drug discovery. The focus of this dissertation is on the development and implementation of novel...
Show moreThe rise of antibiotic resistant microbes (bacteria, fungi, and parasites), combined with the current void of new drugs entering the clinical setting, has created an urgent need for the discovery of new antimicrobials. High-throughput screening (HTS) assays represent a fast and cost-efficient method for identifying new therapeutic compounds and have been the longstanding gold standard for drug discovery. The focus of this dissertation is on the development and implementation of novel methodologies to increase the throughput of target-based HTS by designing assays that allow multiple drug targets to be probed simultaneously. During my graduate studies, I developed three distinct HTS assays. In each of these assays, drug targets were incorporated into synthetic pathways obeying various reaction topologies (e.g., cyclical, parallel, or linear). Each of these reaction topologies conferred specific advantages and limitations to the individual assays. The first assay reconstitutes the bacterial tRNA-dependent pathway for lipid aminoacylation. This two-step pathway combines a tRNA aminoacylation step catalyzed by an aminoacyl-tRNA synthetase (aaRS), and a transferase step, which transfers the amino acid born by the tRNA onto membrane lipids. aaRSs are essential enzymes in all domains of life and represent longstanding drug targets in pathogenic species. The transferase reaction in the pathway is also an appealing drug target since it impacts the cellular permeability of antibiotics. Inhibitors of this reaction could dramatically increase the efficacy of existing therapeutics. The second assay I developed also targets aaRSs, but utilizes a parallel topology that permits the probing of the synthetic and editing activities of up to four aaRSs simultaneously. The third assay utilizes a linear topology that reconstitutes the entire purine salvage pathway from Plasmodium falciparum. Because parasites are unable to synthesize purines de novo, this pathway represents an appealing target for novel antimalarials. Pilot screens using this assay revealed inhibitors for multiple enzymes in the pathway, validating the design of the system. This body of work aims to shift the current paradigm of single-target systems that have historically dominated the HTS field, toward multi-target designs that can be used to more efficiently screen compound libraries against essential pathways in pathogenic microbes.
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Date Issued
2019
Identifier
CFE0007642, ucf:52469
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0007642
Adaptive Architectural Strategies for Resilient Energy-Aware Computing
Title
Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
Creator
Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
Abstract / Description
Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
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Date Issued
2015
Identifier
CFE0006206, ucf:52889
Format
Document (PDF)
PURL
http://purl.flvc.org/ucf/fd/CFE0006206