Current Search: hot electron (x)
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- Title
- INVESTIGATION AND TRADE STUDY ON HOT CARRIER RELIABILITY OF THE PHEMT FOR DC AND RF PERFORMANCE.
- Creator
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Steighner, Jason, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe...
Show moreA unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstrate the performance degradation that occurs after a period of operation in an accelerated stress regime-one hour of high drain voltage, low drain current stress. This stress regime and normal operation regime are then modeled through Sentaurus. Output characteristics are shown along with stress mechanisms within the device. Lastly, a means of simulating a PHEMT post-stress is introduced. The approach taken accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance are then investigated.
Show less - Date Issued
- 2011
- Identifier
- CFE0003994, ucf:48659
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003994
- Title
- CONVENTIONAL AND ZVT SYNCHRONOUS BUCK CONVERTER DESIGN, ANALYSIS, AND MEASUREMENT.
- Creator
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Cory, Mark, Yuan, Jiann, University of Central Florida
- Abstract / Description
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The role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, todayÃÂ's demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses...
Show moreThe role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, todayÃÂ's demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses to a minimum. The power conversion circuitry in a system is a very good place to reduce a large amount of unnecessary loss. This can be done using circuit topologies that are low loss in nature. For low loss and high performance, soft switching topologies have offered solutions in some cases. Also, limited study has been performed on device aging effects on switching mode power converting circuits. The impact of this effect on a converterÃÂ's overall efficiency is theoretically known but with little experimental evidence in support. In this thesis, non-isolated buck type switching converters will be the main focus. This type of power conversion is widely used in many systems for DC to DC voltage step down. Newer methods and topologies to raise converter power efficiency are discussed, including a new synchronous ZVT topology . Also, a study has been performed on device aging effects on converter efficiency. Various scenarios of voltage conversion, switching frequency, and circuit components as well as other conditions have been considered. Experimental testing has been performed in both cases, ZVTÃÂ's benefits and device aging effects, the results of which are discussed as well.
Show less - Date Issued
- 2010
- Identifier
- CFE0003106, ucf:48650
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003106
- Title
- rf power amplifier and oscillator design for reliability and variability.
- Creator
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Chen, Shuyu, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Gong, Xun, Wang, Morgan, University of Central Florida
- Abstract / Description
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CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier...
Show moreCMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable.In this work, a class E power amplifier is designed and laid out using TSMC 0.18 (&)#181;m RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate self-heating effects under different localized heating situations. Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.
Show less - Date Issued
- 2013
- Identifier
- CFE0004664, ucf:49894
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0004664
- Title
- STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES.
- Creator
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MA, JUN, Yuan, Jiann S., University of Central Florida
- Abstract / Description
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In the modern semiconductor world, there is a significant scaling of the transistor dimensions The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused...
Show moreIn the modern semiconductor world, there is a significant scaling of the transistor dimensions The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance. The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device from device level to circuit level; Studying real voltage stress case high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.
Show less - Date Issued
- 2009
- Identifier
- CFE0002856, ucf:48073
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002856
- Title
- RF Circuit Designs for Reliability and Process Variability Resilience.
- Creator
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Kritchanchai, Ekavut, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Wei, Lei, Lin, Mingjie, Chow, Lee, University of Central Florida
- Abstract / Description
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Complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms,...
Show moreComplementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms, such as gate oxide breakdown, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. In addition, process variability becomes a new design paradigm in modern RF circuits.In this Ph.D. work, a class F power amplifier (PA) was designed and analyzed using TSMC 180nm process technology. Its pre-layout and post-layout performances were compared. Post-layout parasitic effect decreases the output power and power-added efficiency. Physical insight of hot electron impact ionization and device self-heating was examined using the mixed-mode device and circuit simulation to mimic the circuit operating environment. Hot electron effect increases the threshold voltage and decreases the electron mobility of an n-channel transistor, which in turn decreases the output power and power-added efficiency of the power amplifier, as evidenced by the RF circuit simulation results. The device self-heating also reduces the output power and power-added efficiency of the PA. The process, voltage, and temperature (PVT) effects on a class AB power amplifier were studied. A PVT compensation technique using a current-source as an on-chip sensor was developed. The adaptive body bias design with the current sensing technique makes the output power and power-added efficiency much less sensitive to process variability, supply voltage variation, and temperature fluctuation, predicted by our derived analytical equations which are also verified by Agilent Advanced Design System (ADS) circuit simulation.Process variations and hot electron reliability on the mixer performance were also evaluated using different process corner models. The conversion gain and noise figure were modeled using analytical equations, supported by ADS circuit simulation results. A process invariant current source circuit was developed to eliminate process variation effect on circuit performance. Our conversion gain, noise figure, and output power show robust performance against PVT variations compared to those of a traditional design without using the current sensor, as evidenced by Monte Carlo statistical simulation.Finally, semiconductor process variations and hot electron reliability on the LC-voltage controlled oscillator (VCO) performance was evaluated using different process models. In our newly designed VCO, the phase noise and power consumptions are resilient against process variation effect due to the use of on-chip current sensing and compensation. Our Monte-Carlo simulation and analysis demonstrate that the standard deviation of phase noise in the new VCO design reduces about five times than that of the conventional design.
Show less - Date Issued
- 2016
- Identifier
- CFE0006131, ucf:51182
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006131
- Title
- CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
- Creator
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Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
Show less - Date Issued
- 2011
- Identifier
- CFE0003595, ucf:48861
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003595
- Title
- TRAFFIC SAFETY ASSESSMENT OF DIFFERENT TOLL COLLECTION SYSTEMS ON EXPRESSWAYS USING MULTIPLE ANALYTICAL TECHNIQUES.
- Creator
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Abuzwidah, Muamer, Abdel-Aty, Mohamed, Radwan, Essam, Uddin, Nizam, University of Central Florida
- Abstract / Description
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Traffic safety has been considered one of the most important issues in the transportation field. Crashes have caused extensive human and economic losses. With the objective of reducing crash occurrence and alleviating crash injury severity, major efforts have been dedicated to reveal the hazardous factors that affect crash occurrence. With these consistent efforts, both fatalities and fatality rates from road traffic crashes in many countries have been steadily declining over the last ten...
Show moreTraffic safety has been considered one of the most important issues in the transportation field. Crashes have caused extensive human and economic losses. With the objective of reducing crash occurrence and alleviating crash injury severity, major efforts have been dedicated to reveal the hazardous factors that affect crash occurrence. With these consistent efforts, both fatalities and fatality rates from road traffic crashes in many countries have been steadily declining over the last ten years. Nevertheless, according to the World Health Organization, the world still lost 1.24 million lives from road traffic crashes in the year of 2013. And without action, traffic crashes on the roads network are predicted to result in deaths of around 1.9 million people, and up to 50 million more people suffer non-fatal injuries annually, with many incurring a disability as a result of their injury by the year 2020. To meet the transportation needs, the use of expressways (toll roads) has risen dramatically in many countries in the past decade. In fact, freeways and expressways are considered an important part of any successful transportation system. These facilities carry the majority of daily trips on the transportation network. Although expressways offer high level of service, and are considered the safest among other types of roads, traditional toll collection systems may have both safety and operational challenges. The traditional toll plazas still experience many crashes, many of which are severe. Therefore, it becomes more important to evaluate the traffic safety impacts of using different tolling systems. The main focus of the research in this dissertation is to provide an up-to-date safety impact of using different toll collection systems, as well as providing safety guidelines for these facilities to promote safety and enhance mobility on expressways. In this study, an extensive data collection was conducted that included one hundred mainline toll plazas located on approximately 750 miles of expressways in Florida. Multiple sources of data available online maintained by Florida Department of Transportation were utilized to identify traffic, geometric and geographic characteristics of the locations as well as investigating and determination of the most complete and accurate data. Different methods of observational before-after and Cross-Sectional techniques were used to evaluate the safety effectiveness of applying different treatments on expressways. The Before-After method includes Na(&)#239;ve Before-After, Before-After with Comparison Group, and Before-After with Empirical Bayesian. A set of Safety Performance Functions (SPFs) which predict crash frequency as a function of explanatory variables were developed at the aggregate level using crash data and the corresponding exposure and risk factors. Results of the aggregate traffic safety analysis can be used to identify the hazardous locations (hot spots) such as traditional toll plazas, and also to predict crash frequency for untreated sites in the after period in the Before-After with EB method or derive Crash Modification Factors (CMF) for the treatment using the Cross-Sectional method. This type of analysis is usually used to improve geometric characteristics and mainly focus on discovering the risk factors that are related to the total crash frequency, specific crash type, and/or different crash severity levels. Both simple SPFs (with traffic volume only as an explanatory variable) and full SPFs (with traffic volume and additional explanatory variable(s)) were used to estimate the CMFs and only CMFs with lower standard error were recommended.The results of this study proved that safety effectiveness was significantly improved across all locations that were upgraded from Traditional Mainline Toll Plazas (TMTP) to the Hybrid Mainline Toll Plazas (HMTP) system. This treatment significantly reduced total, Fatal-and-Injury (F+I), and Rear-End crashes by 47, 46 and 65 percent, respectively. Moreover, this study examined the traffic safety impact of using different designs, and diverge-and-merge areas of the HMTP. This design combines either express Open Road Tolling (ORT) lanes on the mainline and separate traditional toll collection to the side (design-1), or traditional toll collection on the mainline and separate ORT lanes to the side (design-2). It was also proven that there is a significant difference between these designs, and there is an indication that design-1 is safer and the majority of crashes occurred at diverge-and-merge areas before and after these facilities. However, design-2 could be a good temporary design at locations that have low prepaid transponder (Electronic Toll Collection (ETC)) users. In other words, it is dependent upon the percentage of the ETC users. As this percentage increases, more traffic will need to diverge and merge; thus, this design becomes riskier. In addition, the results indicated significant relationships between the crash frequency and toll plaza types, annual average daily traffic, and drivers' age. The analysis showed that the conversion from TMTP to the All-Electronic Toll Collection (AETC) system resulted in an average reduction of 77, 76, and 67 percent for total, F+I, and Property Damage Only (PDO) crashes, respectively; for rear end and Lane Change Related (LCR) crashes the average reductions were 81 and 75 percent, respectively. The conversion from HMTP to AETC system enhanced traffic safety by reducing crashes by an average of 23, 29 and 19 percent for total, F+I, and PDO crashes; also, for rear end and LCR crashes, the average reductions were 15 and 21 percent, respectively. Based on these results, the use of AETC system changed toll plazas from the highest risk sections on Expressways to be similar to regular segments. Therefore, it can be concluded that the use of AETC system was proven to be an excellent solution to several traffic operations as well as environmental and economic problems. For those agencies that cannot adopt the HMTP and the AETC systems, improving traffic safety at traditional toll plazas should take a priority.This study also evaluates the safety effectiveness of the implementation of High-Occupancy Toll lanes (HOT Lanes) as well as adding roadway lighting to expressways. The results showed that there were no significant impact of the implementation of HOT lanes on the roadway segment as a whole (HOT and Regular Lanes combined). But there was a significant difference between the regular lanes and the HOT lanes at the same roadway segment; the crash count increased at the regular lanes and decreased at the HOT lanes. It was found that the total and F+I crashes were reduced at the HOT lanes by an average of 25 and 45 percent, respectively. This may be attributable to the fact that the HOT lanes became a highway within a highway. Moreover adding roadway lighting has significantly improved traffic safety on the expressways by reducing the night crashes by approximately 35 percent.Overall, the proposed analyses of the safety effectiveness of using different toll collection systems are useful in providing expressway authorities with detailed information on where countermeasures must be implemented. This study provided for the first time an up-to-date safety impact of using different toll collection systems, also developed safety guidelines for these systems which would be useful for practitioners and roadway users.
Show less - Date Issued
- 2014
- Identifier
- CFE0005751, ucf:50100
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0005751